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Please refer to our discourse or https://gitter.im/myhdl/myhdl
The clock driver function clk_driver drives the clock signal. If defines a generator that continuously toggles a clock signal after a certain delay. A new value of a signal is specified by assigning to its next attribute. This is the MyHDL equivalent of the VHDL signal assignment and the Verilog non-blocking assignment.
The text was updated successfully, but these errors were encountered:
Please refer to our discourse or https://gitter.im/myhdl/myhdl
The clock driver function clk_driver drives the clock signal. If defines a generator that continuously toggles a clock signal after a certain delay. A new value of a signal is specified by assigning to its next attribute. This is the MyHDL equivalent of the VHDL signal assignment and the Verilog non-blocking assignment.
The text was updated successfully, but these errors were encountered: