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Starred repositories
TUI Application to manage Obsidian notes directly from the terminal
Generates a SystemVerilog assertion interface for a given SV RTL design
Repository of FPGA from Zero to Hero - Live and Free FPGA/SoC Lectures on YouTube (www.youtube.com/@falsepaths)
HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-slang.
GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
This is the playbook for "code-with" customer or partner engagements
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
Python packages providing a library for Verification Stimulus and Coverage
Python GUIs for Humans! PySimpleGUI is the top-rated Python application development environment. Launched in 2018 and actively developed, maintained, and supported in 2024. Transforms tkinter, Qt, …
An open-source HDL register code generator fast enough to run in real time.
Communication framework for RTL simulation and emulation.
This is the Rust course used by the Android team at Google. It provides you the material to quickly teach Rust.
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
❄️ Visual editor for open FPGA boards
List of awesome open source hardware tools, generators, and reusable designs
A Hardware Description Language based on the Rust Programming Language
A framework for writing FPGA firmware using the Rust Programming Language