8000 GitHub - martinmaly21/ELEC374: A simple RISC computer built using Verilog
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.gitignore
.gitignore
 
 
ALU.bsf
ALU.bsf
 
 
ALU.v
ALU.v
 
 
BUS.bsf
BUS.bsf
 
 
BUS.v
BUS.v
 
 
CON_FF.v
CON_FF.v
 
 
DesignProject.bdf
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DesignProject.qpf
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DesignProject.qsf
DesignProject.qsf
 
 
DesignProject_tb.bsf
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DesignProject_tb.v
DesignProject_tb.v
 
 
IncPCModule.bsf
IncPCModule.bsf
 
 
IncPCModule.v
IncPCModule.v
 
 
LICENSE
LICENSE
 
 
MAR.v
MAR.v
 
 
MDR.bsf
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MDR.v
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README.md
README.md
 
 
Register.bsf
Register.bsf
 
 
Register_0.v
Register_0.v
 
 
add_32_gate.bsf
add_32_gate.bsf
 
 
add_32_gate.v
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addi_tb.v
addi_tb.v
 
 
and_32_gate.bsf
and_32_gate.bsf
 
 
and_32_gate.v
and_32_gate.v
 
 
andi_tb.v
andi_tb.v
 
 
brmi_tb.v
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brnz_tb.v
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brpl_tb.v
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brzr_tb.v
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control_unit.v
control_unit.v
 
 
datapath.bsf
datapath.bsf
 
 
datapath.v
datapath.v
 
 
div_32_gate.v
div_32_gate.v
 
 
inPort.v
inPort.v
 
 
inPort_tb.v
inPort_tb.v
 
 
jal_tb.v
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jr_tb.v
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ld_tb.v
ld_tb.v
 
 
ldi_tb.v
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memory.hex
memory.hex
 
 
mfhi_tb.v
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mflo_tb.v
mflo_tb.v
 
 
mul_32_gate.v
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neg_32_gate.v
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not_32_gate.bsf
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not_32_gate.v
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or_32_gate.bsf
or_32_gate.bsf
 
 
or_32_gate.v
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ori_tb.v
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outPort.v
outPort.v
 
 
outPort_tb.v
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ram.v
ram.v
 
 
ram2.bsf
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ram2.v
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ram2_bb.v
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ram2_inst.v
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reg_32_bits.bsf
reg_32_bits.bsf
 
 
register.v
register.v
 
 
rol_32_gate.v
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ror_32_gate.v
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select_encode_logic.v
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shl_32_gate.bsf
shl_32_gate.bsf
 
 
shl_32_gate.v
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shr_32_gate.bsf
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shr_32_gate.v
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st_tb.v
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sub_32_gate.bsf
sub_32_gate.bsf
 
 
sub_32_gate.v
sub_32_gate.v
 
 

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ELEC 374

Final project for ELEC 374 Digital Systems Engineering W22 to design a Simple RISC Computer using Verilog.

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ELEC374 is available under the MIT license. See the LICENSE file for more info.

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A simple RISC computer built using Verilog

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