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The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
📈 A small, fast chart for time series, lines, areas, ohlc & bars
A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)
A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
Digital logic design tool and simulator
The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor mo…
You like pytorch? You like micrograd? You love tinygrad! ❤️
Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
Vector processor for RISC-V vector ISA
A template project for beginning new Chisel work
Hammer: Highly Agile Masks Made Effortlessly from RTL
Verilator open-source SystemVerilog simulator and lint system
training labs and examples
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol
Contains the code examples from The UVM Primer Book sorted by chapters.
A pandoc LaTeX template to convert markdown files to PDF or LaTeX.