Stars
Re-coded Xilinx primitives for Verilator use
A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one
Like VexRiscv, but, Harder, Better, Faster, Stronger
Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from https://github.com/shioyadan/Konata/releases
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…
21st century electronic design automation tools, written in Rust.
A Hardware Description Language that doesn't make you want to pull your hair out | read-only mirror of https://gitlab.com/spade-lang/spade/
HazardFlow: Modular Hardware Design of Pipelined Circuits with Hazards IMPORTANT: DON'T FORK!
DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
A unified interface for reading and writing object file formats
Setup scripts and files needed to compile CoreMark on RISC-V
Easy flamegraphs for Rust projects and everything else, without Perl or pipes <3
Allo: A Programming Model for Composable Accelerator Design
어느 플랫폼에서든 사용할 수 있는 system-ui 대체 글꼴 | A system-ui alternative font for all cross-platform
A core language for rule-based hardware design 🦑
A Platform for High-Level Parametric Hardware Specification and its Modular Verification
wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.
Native Rust implementation of the FST waveform format from GTKWave.
100 Gbps TCP/IP stack for Vitis shells
Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Generate interface between Clash and Verilator
FPGA board-level debugging and reverse-engineering tool