bluecore is 5-stage pipelined RV64IMACZicsr_Zifencei_Zicntr CPU written in Veryl.
It supports Sv39.
Do you want to write CPU in Veryl?
Yes! you can see instruction.
- rv64u(i/m/a/c)-(p/v)-*
- rv64(s/m)i-p-*
require Verilator
$ cd core
$ make build
$ make sim
# target is objdir/simcompile test.c
$ riscv64-unknown-elf-gcc -nostartfiles -nostdlib -T test/link.ld test.c test/entry.S convert elf to hex format
$ riscv64-unknown-elf-objcopy a.out -O binary test.bin
$ python3 test/bin2hex.py 8 test.bin > test.bin.hexrun simulator
$ obj_dir/sim bootrom.hex test.bin.hex