This repository contains the ODMB7/5 firmware in development.
Most (if not all) of the sub-modules are shared between ODMB7 and ODMB5, with generic variable NCFEB to define any difference in behaviors between them. The top modules of ODMB7/5 firmwares are contained in odmb7_dev_top.vhd and odmb5_dev_top.vhd, respectively. Their project may also contain different set of files and IPs, managed by different Vivado projects, odmb7_ucsb_dev.xpr and odmb5_ucsb_dev.xpr.
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The naming of the signals in the top modules follow the signal names that connected directly to the FPGA in the respective schematics as much as possible, except when they can be improved to give more clarity. In such case (e.g.
C_TDO-->DCFEB_TDO,DONE-->DCFEB_DONE), the actual signal name is listed in the comment of the top file. -
The position of the pin (which Bank it is connected to) shall be attached as comment in the entity declaration.
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Every connected signal is assigned a corresponding signal in the top module entity declaration to keep the record, even if they are unused. An exception is made to the
EMCCLKpin and the primary PROM programming pins.
The HDL code specific for simulation are under the simulation folder. This will contain the simulation wrapper for ODMB7/5 firmware, the simulated VME, DCFEBs, and possibly other devices in the future. LUTs are used to provide VME commands to the ODMB7/5.
The most recent config file for the clock synthesizer on board, as well as the human readable documentation of them are placed under the clock_configs directory.
Currently, the firmware is developed under the assumption that config similar to ZL30267_4freqs_211115.mfg is used.
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Port ODMB_VME from ODMB
- COMMAND_MODULE
- Device 1: CFEBJTAG
- Import VME simulation
- Import DCFEB simulation (only user code reading)
- Device 2: ODMBJTAG
- Device 3: VMEMON
- Device 4: VMECONFREGS
- Device 5: TESTFIFOS --> CLOCK_MON
- Device 6: SPI_PORT
- CFG Register upload/download
- Write Command FIFO
- Read readback FIFO
- SPI state machine commands
- Read SPI status/timer
- Device 7: SYSTEM_MON
- Import SYSMON module for currents
- Develope voltage monitoring with SPI
- Device 8: LVDBMON
- Import LVDB module
- Device 9: SYSTEM_TEST
- Import OTMB PRBS test
- Import the Optical PRBS tests
- SPI_CTRL
- Read/write/erase PROM commands
- Other PROM commands (status/lock/unlock/check)
- Timer commands
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Port ODMB_CTRL from ODMB
- Port CALIBTRG
- Port TRGCNTRL
- Port CAFIFO
- Port CONTROL_FSM
- Port PCFIFO
- Run3 logic tested
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Configure optical interfaces
- (x)DCFEB interface
- ALCT interface
- GBT interface between ALCT-LX100 and ODMB7
- Dual link 8B/10B between ALCT-LX150 and ODMB5
- SPY interface
- DDU communication logic for Run3 DAQ config
- PC communication logic
- FED interface
- Quad-link data transmission to the FED for ODMB7
- Tri-link and dual-link data transmission for ODMB5
- GBT interface for back pressure signal from FED
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Wrap up dangling logics in the top file
- ODMB clocking logic
- ODMB status monitoring logic
- ODMB reset and init logic
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Develop Run4 DAQ logic
After cloning the project, edit the project/odmb7_ucsb_dev.xpr and project/odmb5_ucsb_dev.xpr
so that the project path is correct. An example is shown below,
<Project Version="7" Minor="44" Path="/higgs-data/jbkim/odmb/odmb_daq/odmb7_port_testing/project/odmb7_ucsb_dev.xpr">
To simulate the project, first Run Synthesis to generate the IP files, and then Run Simulation.