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D-curs-D / Inverter-design-and-analysis-using-sky130pdk

Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools

Shell 110 23 Updated May 14, 2022

efabless / OpenLane

Forked from The-OpenROAD-Project/OpenLane

This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is an automated RTL to GDSII flow based on several components i…

Python 152 39 Updated Jun 1, 2024

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Python 1,506 396 Updated Feb 26, 2025

JonathanJing / Asynchronous-FIFO

Asynchronous fifo in verilog

Verilog 35 21 Updated Mar 20, 2016
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