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@oscc-ip OSCC IP Project

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    6 repositories

    • artifact

      Public
      A repository provides build artifacts for various open-source EDA tools.
      openstaieda
      0•1•0•0•Updated Jun 26, 2025Jun 26, 2025

    • sdram

      Public
      An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.
      fpgaverilogsdramaxi4tapeout
      Scala
      •2•18•0•1•Updated May 12, 2025May 12, 2025

    • .github

      Public
      GNU General Public License v3.0
      •0•1•0•0•Updated Apr 20, 2025Apr 20, 2025

    • nangate

      Public
      Nangate Open Cell Library
      Verilog
      •
      Apache License 2.0
      •0•3•0•0•Updated Jan 28, 2025Jan 28, 2025

    • cl2-chisel

      Public
      Scala
      •
      Other
      •0•1•0•0•Updated Jan 8, 2025Jan 8, 2025

    • cl2

      Public
      SystemVerilog
      •
      Mulan Permissive Software License, Version 2
      •0•1•0•0•Updated Jan 8, 2025Jan 8, 2025
    0