GitHub - abdullah-qureshi/NuCore: This project is a processer design with Verilog HDL for an undergraduate course. The processor is built in pipelined stage and divided to 5 stages which are instruction fetch (IF), instruction decode (ID), instruction execution (EX), memory (MEM) and write back (WB).

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This project is a processer design with Verilog HDL for an undergraduate course. The processor is built in pipelined stage and divided to 5 stages which are instruction fetch (IF), instruction decode (ID), instruction execution (EX), memory (MEM) and write back (WB).

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Name	Name	Last commit date
Latest commit History 1 Commit
ALU.v	ALU.v
ALU.v.bak	ALU.v.bak
InstDecoder.v	InstDecoder.v
InstDecoder.v.bak	InstDecoder.v.bak
InstQueue.v	InstQueue.v
InstQueue.v.bak	InstQueue.v.bak
PC.v	PC.v
PC.v.bak	PC.v.bak
c5_pin_model_dump.txt	c5_pin_model_dump.txt
nucore.qpf	nucore.qpf
nucore.qsf	nucore.qsf
nucore.qsf.bak	nucore.qsf.bak
nucore.qws	nucore.qws
nucore.v	nucore.v
nucore.v.bak	nucore.v.bak
nucore_nativelink_simulation.rpt	nucore_nativelink_simulation.rpt
nucore_tb.v	nucore_tb.v
nucore_tb.v.bak	nucore_tb.v.bak
out_reg.v	out_reg.v
out_reg.v.bak	out_reg.v.bak
pipeline_reg.v	pipeline_reg.v
pipeline_reg.v.bak	pipeline_reg.v.bak
register_file.v	register_file.v
register_file.v.bak	register_file.v.bak
register_tb.v	register_tb.v
register_tb.v.bak	register_tb.v.bak
stall_reg.v	stall_reg.v
stall_reg.v.bak	stall_reg.v.bak
zero_reg.v	zero_reg.v	� 5148 �
zero_reg.v.bak	zero_reg.v.bak