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A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard
FPGA-based neural network inference project for 2020 DAC System Design Contest
OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.
OpenCL for Nets - A Deep Learning Framework based on OpenCL, written by C++. Supports popular MLP, RNN(LSTM), CNN(ResNet). Friendly debugger. Transparent data. No library dependencies. 基于OpenCL的深度学…
Fast Synchronization-Free Algorithms for Parallel Sparse Triangular Solves with Multiple Right-Hand Sides (SpTRSM)
Implementation of COO, CSR, CSC, SSS and TJDS sparse matrix formats.
A Vector Caching Scheme for Streaming FPGA SpMV Accelerators
Vivado 2018.1 project implementing handwritten digits recognition for Xilinx Zynq-7000 SoC (Zybo board) based on hardware-accelerated (FPGA) SLINK clustering algorithm.
A collection of Zynq Zedboard applications for Linux and baremetal.
Example program for computing a sparse matrix-vector multiplication with a matrix in the compressed sparse row (CSR) format.
EVALUATING THE PERFORMANCE OF COMPUTING PLATFORMS USING A SET OF COMPUTE KERNELS
Some experiments of using OpenCL on Intel FPGAs