10000 aswaterman (Andrew Waterman) / Starred · GitHub
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521 followers · 31 following

Achievements

Achievement: Starstruckx4Achievement: Pair Extraordinairex2Achievement: QuickdrawAchievement: YOLOAchievement: Pull Sharkx4Achievement: Arctic Code Vault Contributor

Achievements

Achievement: Starstruckx4Achievement: Pair Extraordinairex2Achievement: QuickdrawAchievement: YOLOAchievement: Pull Sharkx4Achievement: Arctic Code Vault Contributor

Organizations

@ucb-bar @riscv @sifive @freechipsproject @chipsalliance

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Stars

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aswaterman / trainwreck

Original RISC-V 1.0 implementation. Not supported.

Verilog 41 14 Updated Oct 4, 2018

Codeusa / Borderless-Gaming

Play your favorite games in a borderless window; no more time consuming alt-tabs.

C# 5,958 555 Updated Aug 5, 2024

rui314 / mold

mold: A Modern Linker 🦠

C++ 15,438 506 Updated Jul 15, 2025

riscv-software-src / riscv-isa-sim

Spike, a RISC-V ISA Simulator

C 2,756 950 Updated Jul 8, 2025

riscv / riscv-isa-manual

RISC-V Instruction Set Manual

TeX 4,161 722 Updated Jul 15, 2025

chipsalliance / chisel

Chisel: A Modern Hardware Design Language

Scala 4,341 632 Updated Jul 15, 2025

chipsalliance / firrtl

Flexible Intermediate Representation for RTL

Scala 747 181 Updated Aug 20, 2024

sifive / freedom

Source files for SiFive's Freedom platforms

Scala 1,125 285 Updated Jul 17, 2021

chipsalliance / rocket-chip

Rocket Chip Generator

Scala 3,496 1,174 Updated May 27, 2025
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