Tags: bgergely0/byoc
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OpenPiton Release 13 (19-10-23-r13) New: - Support for Amazon AWS F1 - Support for BittWare XUP-P3R FPGA board - Tursi pickling tool based on FuseSoC - New, higher performance AXI4 memory controller (and AXI4 memory zeroing) - Exponential back-off for Ariane LR/SC See changelog and history for more details.
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Oct 23, 2019 - dd1e210
- zip < 8000 /a>
- tar.gz
OpenPiton Release 12 (19-06-06-r12) New: - Addition of Ariane FPU for FPGA - Simulation of OpenPiton+Ariane with VCS - Simulation of OpenPiton+Ariane with Verilator - Ethernet support for Ariane on Genesys2 and Nexys Video - AXI4 memory controller option on VC707 Important tool changes: - Vivado 2016.4 or newer now required for SPARC - m4 preprocessor updated. Re-source piton_settings.bash to set M4PATH - Removed some 32 bit libraries and replaced with 64 bit. This changes some dependencies See changelog and history for more details.
OpenPiton Release 11 (19-03-19-r11) - SMP Linux boots on FPGA with OpenPiton+Ariane - Support for Verilator simulation See changelog and history for more details
OpenPiton Release 10 (18-11-29-r10) These are all the changes needed to integrate Ariane into OpenPiton to create OpenPiton+Ariane. The Ariane L1 cache system has been modified to integrate with Openpiton's P-Mesh cache system at the L1.5 cache. Simulation support for Ariane RISC-V tests is also included. FPGA support is a work-in-progress. Check out the README.md for more information on the integration.
OpenPiton Release 9 (18-11-20-r9) These are all the changes related to the integration of the PicoRV32 core with the OpenPiton framework to create "JuxtaPiton". They enable the instantiation of the framework using OpenPiton and PicoRV32 cores in simulation and on FPGA. Designs can be implemented with just SPARC cores, just PicoRV32 cores, or a mix. Changes include: -Adding the PicoRV32 core to the hierarchy -Adding two shims (pico_decoder and l15_picoencoder) that sit between the PicoRV32 core and the L1.5 cache that enable PicoRV32 to interface with the OpenPiton cache system -Modifications to various instantiations throughout tile and L1.5 to instantiate PicoRV32 or OpenPiton structures as appropriate -Modifications to infrastructure files for FPGA and simulation to configure the instantiation of PicoRV32 or OpenPiton cores --- The changes also add support for running riscv assembly tests in simulation. The tests used are the same as those provided with picorv32, rather than the ones provided in riscv-tests, but I think the difference is minor. This passes all of the provided assembly tests. You can run them using `sims -group=pico_tile1 -sim_type=vcs` (replacing vcs with icv/ncv/msm if you prefer a different compiler). If you want to add a new test, throw it in `piton/verif/diag/assembly/riscv/pico/` and make sure you use a capital S for the test filename's extension. This isn't intended to be robust to arbitrary tests you write. A later commit should at least support the C benchmarks that come as part of riscv-tests. Small issue: simple.S actually doesn't pass but that's just some because there's no code produced for the pass or fail labels. --- The final thing included is support for RISC-V AMO ops (but not LR/SC) which are performed in the L2 cache.
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