VR16, a basic RISC processor designed and written in verilog. As time permits, this will be made better and backend design will also be updated.
- each instruction is 16-bit.
- 4 general purpose registers (r0, r1, r2, r3).
- runs on custom instruction set architecture called vr-isa.
vr-asmas assembly andvrscriptfor writing easier code to run on the cpu.
Warning
The isa is very much work in progress, so things are subject to change.
Documentation for vr-asm and vrscript may or may not be up-to-date due to extensive prematurity of their presence.
On how to run this project in your local machine.
- Install WSL and install
gtkwaveandiverilog. - Setup venv in root directory.
- Run
./compile.shand then./sim.shto view the rtl waveforms.
- Install
gtkwaveandiverilog. - Setup venv in root directory.
- Run
./compile.shand then./sim.shto view the rtl waveforms.
There are three parts to this CPU:
- frontend
- backend
- toolchain
- Frontend deals with the synthesizable code written in verilog, the rtl and the corresponding testbenches, which are licensed under
GPLv3. - Backend (will start soon) deals with the actual physical design of the cpu, which will be licensed under the
CERN-OHL-S. - Toolchain deals with the software side of the project, the
assembler/andcompiler/which makes programming on the CPU, which also come underGPLv3.