8000 Add resetType to inline test TestParameters by tmckay-sifive · Pull Request #4789 · chipsalliance/chisel · GitHub
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Add resetType to inline test TestParameters #4789

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Merged
merged 6 commits into from
Mar 13, 2025
Merged

Add resetType to inline test TestParameters #4789

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0b4c9af
add resetType to TestParameters
tmckay-sifive Feb 25, 2025
bdd10db
add test
tmckay-sifive Mar 12, 2025
f4bd246
format
tmckay-sifive Mar 12, 2025
aeb1ef1
add test for RawModule
tmckay-sifive Mar 12, 2025
ce7e2a2
use modern filecheck methods
tmckay-sifive Mar 12, 2025
5d2d731
Merge remote-tracking branch 'origin/main' into tmckay/inline-test-re…
tmckay-sifive Mar 12, 2025
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16 changes: 13 additions & 3 deletions src/main/scala/chisel3/experimental/inlinetest/InlineTest.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,9 @@ class TestParameters[M <: RawModule, R] private[inlinetest] (
/** A Definition of the DUT module. */
val dutDefinition: Definition[M],
/** The body for this test, returns a result. */
val testBody: Instance[M] => R
val testBody: Instance[M] => R,
/** The reset type of the DUT module. */
val resetType: Option[Module.ResetType.Type]
) {
final def desiredTestModuleName = s"test_${dutName}_${testName}"
}
Expand Down Expand Up @@ -50,7 +52,11 @@ object TestHarness {
* @tparam R the type of the result returned by the test body
*/
trait Module[M <: ChiselRawModule, R] extends RawModule[M, R] { this: ChiselModule =>
override def resetType = Module.ResetType.Synchronous
override def resetType = test.resetType match {
case Some(rt @ Module.ResetType.Synchronous) => rt
case Some(rt @ Module.ResetType.Asynchronous) => rt
case _ => Module.ResetType.Synchronous
}
}
}

Expand Down Expand Up @@ -110,7 +116,11 @@ trait HasTests[M <: RawModule] { module: M =>
testName: String
)(testBody: Instance[M] => R)(implicit th: TestHarnessGenerator[M, R]): Unit =
elaborateParentModule { moduleDefinition =>
val test = new TestParameters[M, R](desiredName, testName, moduleDefinition, testBody)
val resetType = module match {
case module: Module => Some(module.resetType)
case _ => None
}
val test = new TestParameters[M, R](desiredName, testName, moduleDefinition, testBody, resetType)
th.generate(test)
}
}
81 changes: 70 additions & 11 deletions src/test/scala/chiselTests/experimental/InlineTestSpec.scala
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Expand Up @@ -10,6 +10,8 @@ import circt.stage.ChiselStage
import org.scalatest.flatspec.AnyFlatSpec
import org.scalatest.matchers.should.Matchers

import circt.stage.ChiselStage.emitCHIRRTL

class TestResultBundle extends Bundle {
val finish = Output(Bool())
val code = Output(UInt(8.W))
Expand Down Expand Up @@ -67,7 +69,10 @@ class ProtocolMonitor(bundleType: ProtocolBundle) extends Module {
}

@instantiable
class ModuleWithTests(ioWidth: Int = 32) extends Module with HasMonitorSocket with HasTests[ModuleWithTests] {
class ModuleWithTests(ioWidth: Int = 32, override val resetType: Module.ResetType.Type = Module.ResetType.Synchronous)
extends Module
with HasMonitorSocket
with HasTests[ModuleWithTests] {
@public val io = IO(new ProtocolBundle(ioWidth))

override val monProbe = makeProbe(io)
Expand Down Expand Up @@ -112,42 +117,50 @@ class ModuleWithTests(ioWidth: Int = 32) extends Module with HasMonitorSocket wi
}
}

class InlineTestSpec extends AnyFlatSpec with Matchers with FileCheck {
@instantiable
class RawModuleWithTests(ioWidth: Int = 32) extends RawModule with HasTests[RawModuleWithTests] {
@public val io = IO(new ProtocolBundle(ioWidth))
io.out := io.in
test("foo") { instance =>
instance.io.in := 3.U(ioWidth.W)
assert(instance.io.out === 3.U): Unit
}
}

class InlineTestSpec extends AnyFlatSpec with FileCheck {
it should "generate a public module for each test" in {
ChiselStage
.emitCHIRRTL(new ModuleWithTests)
.fileCheck()(
"""
emitCHIRRTL(new ModuleWithTests).fileCheck()(
"""
| CHECK: module ModuleWithTests
| CHECK: output monProbe : Probe<{ in : UInt<32>, out : UInt<32>}>
|
| CHECK: public module test_ModuleWithTests_foo
| CHECK-NEXT: input clock : Clock
| CHECK-NEXT: input reset : UInt<1>
| CHECK-NEXT: input reset
| CHECK: inst dut of ModuleWithTests
|
| CHECK: public module test_ModuleWithTests_bar
| CHECK-NEXT: input clock : Clock
| CHECK-NEXT: input reset : UInt<1>
| CHECK-NEXT: input reset
| CHECK: inst dut of ModuleWithTests
|
| CHECK: public module test_ModuleWithTests_with_result
| CHECK-NEXT: input clock : Clock
| CHECK-NEXT: input reset : UInt<1>
| CHECK-NEXT: input reset
| CHECK-NEXT: output result : { finish : UInt<1>, code : UInt<8>}
| CHECK: inst dut of ModuleWithTests
|
| CHECK: public module test_ModuleWithTests_with_monitor
| CHECK-NEXT: input clock : Clock
| CHECK-NEXT: input reset : UInt<1>
| CHECK-NEXT: input reset
| CHECK: inst dut of ModuleWithTests
| CHECK: inst monitor of ProtocolMonitor
| CHECK-NEXT: connect monitor.clock, clock
| CHECK-NEXT: connect monitor.reset, reset
| CHECK-NEXT: connect monitor.io.out, read(dut.monProbe).out
| CHECK-NEXT: connect monitor.io.in, read(dut.monProbe).in
"""
)
)
}

it should "compile to verilog" in {
Expand All @@ -163,4 +176,50 @@ class InlineTestSpec extends AnyFlatSpec with Matchers with FileCheck {
"""
)
}

it should "emit the correct reset types" in {
def fileCheckString(resetType: String) =
s"""
| CHECK: module ModuleWithTests
| CHECK-NEXT: input clock : Clock
| CHECK-NEXT: input reset : ${resetType}
|
| CHECK: public module test_ModuleWithTests_foo
| CHECK-NEXT: input clock : Clock
| CHECK-NEXT: input reset : ${resetType}
|
| CHECK: public module test_ModuleWithTests_bar
| CHECK-NEXT: input clock : Clock
| CHECK-NEXT: input reset : ${resetType}
|
| CHECK: public module test_ModuleWithTests_with_result
| CHECK-NEXT: input clock : Clock
| CHECK-NEXT: input reset : ${resetType}
|
| CHECK: public module test_ModuleWithTests_with_monitor
| CHECK-NEXT: input clock : Clock
| CHECK-NEXT: input reset : ${resetType}
"""

emitCHIRRTL(new ModuleWithTests(resetType = Module.ResetType.Synchronous)).fileCheck()(
fileCheckString("UInt<1>")
)
emitCHIRRTL(new ModuleWithTests(resetType = Module.ResetType.Asynchronous)).fileCheck()(
fileCheckString("AsyncReset")
)
emitCHIRRTL(new ModuleWithTests(resetType = Module.ResetType.Default)).fileCheck()(
fileCheckString("UInt<1>")
)

emitCHIRRTL(new RawModuleWithTests()).fileCheck()(
"""
| CHECK: module RawModuleWithTests
| CHECK-NEXT: output io
|
| CHECK: public module test_RawModuleWithTests_foo
| CHECK-NEXT: input clock : Clock
| CHECK-NEXT: input reset : UInt<1>
"""
)
}
}
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