8000 RISC-V implementation by HanyzPAPU · Pull Request #25 · d-iii-s/msim · GitHub
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RISC-V implementation #25

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Merged
merged 416 commits into from
Mar 14, 2023
Merged

RISC-V implementation #25

merged 416 commits into from
Mar 14, 2023

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HanyzPAPU
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Cleaned version of the full RISC-V RV32IMA implementation.

HanyzPAPU added 30 commits April 27, 2022 16:44
@HanyzPAPU
jalr disassembly
2477e33
@HanyzPAPU
better target dissasembly and jump comment
2dc9f13
@HanyzPAPU
branch dissasembly
3a9d4b5
@HanyzPAPU
immediate shift dissasembly
c9c7b38
@HanyzPAPU
m extension instructions skeleton
a7d8fe2
@HanyzPAPU
m instr decode
b2a90f9
@HanyzPAPU
M instr decode unit tests
41dc5c4
@HanyzPAPU
m extension implemented
1772bcb
@HanyzPAPU
m-extension test
9d208b4
@HanyzPAPU
fixed sign extension bug
8a7b9d6
@HanyzPAPU
M instr disassembly
9238ec7
@HanyzPAPU
high mul dissasembly
10000
98b564a
@HanyzPAPU
amo opcodes
dd7b95f
@HanyzPAPU
removed op-32 decode
8dcdf96
@HanyzPAPU
A extension instructions skeleton
d2f6ecd
@HanyzPAPU
renamed func to funct
6e8b0ee
@HanyzPAPU
amo decode
beb29d8
@HanyzPAPU
amo decode only 32-bit
3794f85
@HanyzPAPU
amo decode unit tests
bef4ca5
@HanyzPAPU
amo computational instructions implemented
56e7dde
@HanyzPAPU
amo instruction mnemonics decode
132fe92
@HanyzPAPU
amo mnemonics
8a38481
@HanyzPAPU
amo test
4031778
@HanyzPAPU
added rv_cpu_ops
ccf0ebb
@HanyzPAPU
added lr and cs implementation
b17c576
@HanyzPAPU
lr/cs test
a186f74
@HanyzPAPU
fixed write to wrong register
4e53e35
@HanyzPAPU
more complex lr/sc tests
7fd5821
@HanyzPAPU
fixed short write bug
9c1562d
@HanyzPAPU
consultation questions mk. 2
240668c
@HanyzPAPU
added no-riscv-attribute flag to compilation
cbe7d58
@HanyzPAPU
added gcc build notes
38f3f65
@HanyzPAPU
reduced the length of the C demonstration
a6136ae
@HanyzPAPU
make timer interrupts pending on writes to the appropriate CSRs/memor…
b51f34f 
…y mapped regs
@HanyzPAPU
added an assert
9b0d87e
@HanyzPAPU
added matrix multiplication example
9140cfe
@HanyzPAPU
bigger stack
ce654b1
@HanyzPAPU
added stress tests with some measurements
6906401
@HanyzPAPU
added stress tests with some measurements
f4deaba
@HanyzPAPU
added compiled stress and demo binaries
f6fff06
@HanyzPAPU
added native measurements]
28ebb43
@HanyzPAPU
removed comment
df358da
@HanyzPAPU
removed standard import
cdba798
@HanyzPAPU
recompiled
95a1ae2
@HanyzPAPU
changed to demonstration
b78aa81
@HanyzPAPU
removed comment
083a864
@HanyzPAPU
added myself as author
1e09bfb
@HanyzPAPU
changed readme
556a42f
@HanyzPAPU
fixed mbe and sbe
2574a2f
@HanyzPAPU
added clarifying comment
bfc50b1
@HanyzPAPU
added more debugging instructions
041a34a
@HanyzPAPU
added more debugging instructions
c974100
@HanyzPAPU
fixed SPP privilege bug
16e2b5c
@HanyzPAPU
added privilege mode info to regdump
2b9746f
@HanyzPAPU
fixed tests
620c197
@HanyzPAPU
Merge branch 'master' of https://github.com/HanyzPAPU2/msim_clean
d593170
This was referenced Mar 13, 2023
Closed
Closed
@vhotspur vhotspur marked this pull request as ready for review March 14, 2023 12:26
@vhotspur vhotspur merged commit ad4ff74 into d-iii-s:master Mar 14, 2023
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@HanyzPAPU @vhotspur
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