PyTorch implementation of Designing Network Design Spaces by Ilija Radosavovic, Raj Prateek Kosaraju, Ross Girshick, Kaiming He, and Piotr Dollár.
Compared to the official codebase, this repository follows the torchvision's ResNeXt style, which is expected to be more easily interpreted and utilized by pre-existing downstream applications.
We train the following models on 8x TITAN XP GPUs with 12G VRAM. During the first five epochs, we linearly ramp up the learning rate from 0.1.
| Model | Params (M) | GFLOPs | Batch size | Top-1 acc (%) (our impl.) | Top-1 acc (%) (official) |
|---|---|---|---|---|---|
| RegNetX-200M | 2.685 | 0.199 | 1024 | 68.210 | 68.9 |
| RegNetX-400M | 5.158 | 0.398 | 1024 | 72.278 | 72.7 |
| RegNetX-600M | 6.196 | 0.601 | 1024 | 73.862 | 74.1 |
| RegNetX-800M | 7.260 | 0.800 | 1024 | 74.940 | 75.2 |
| RegNetX-1.6G | 9.190 | 1.603 | 1024 | 76.706 | 77.0 |
| RegNetX-3.2G | 15.296 | 3.177 | 512 | 78.188 | 78.3 |
| RegNetX-4.0G | 22.118 | 3.965 | 512 | 78.690 | 78.6 |
| RegNetX-6.4G | 26.209 | 6.460 | 512 | 79.152 | 79.2 |
| RgeNetX-8.0G | 39.573 | 7.995 | 512 | 79.380 | 79.3 |
| RegNetX-12G | 46.106 | 12.087 | 256 | 79.998 | 79.7 |
| RegNetX-16G | 54.279 | 15.941 | 256 | 80.118 | 80.0 |
| RegNetX-32G | 107.812 | 31.736 | 256 | 80.516 | 80.5 |
@InProceedings{Radosavovic_2020_CVPR,
author = {Radosavovic, Ilija and Kosaraju, Raj Prateek and Girshick, Ross and He, Kaiming and Doll{\'a}r, Piotr},
title = {Designing Network Design Spaces},
booktitle = {The IEEE Conference on Computer Vision and Pattern Recognition (CVPR)},
month = {June},
year = {2020}
}