Stars
An assignment for computer network course taught by Shen Jian
A DDR2 memory interface for the Digilent Nexys4 board that does not rely on the Xilinx MIG
A pipelined MIPS CPU supporting 31 MIPS instructions, interrupt and cache.
A single cycle CPU running on Xilinx Spartan 6 XC6LX16-CS324, supporting 31 MIPS instructions.
Final Project of Spring 2018 Artificial Intelligence at Tongji Univ.
A chess library for Python, with move generation and validation, PGN parsing and writing, Polyglot opening book reading, Gaviota tablebase probing, Syzygy tablebase probing, and UCI/XBoard engine c…
**MOVED TO https://github.com/LeelaChessZero/leela-chess ** A chess adaption of GCP's Leela Zero
Chess reinforcement learning by AlphaGo Zero methods.