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vunit Public
Forked from VUnit/vunitVUnit is a unit testing framework for VHDL/SystemVerilog
VHDL Other UpdatedDec 10, 2024 -
Cores-SweRV-EH2 Public
Forked from chipsalliance/Cores-VeeR-EH2SystemVerilog Apache License 2.0 UpdatedMay 18, 2021 -
ariane Public
Forked from openhwgroup/cva6Ariane is a 6-stage RISC-V CPU capable of booting Linux
SystemVerilog Other UpdatedJan 18, 2021 -
Cores-SweRV-EL2 Public
Forked from chipsalliance/Cores-VeeR-EL2SweRV EL2 Core
SystemVerilog Apache License 2.0 UpdatedNov 26, 2020 -
fpnew Public
Forked from openhwgroup/cvfpuParametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
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ibex Public
Forked from lowRISC/ibexIbex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
SystemVerilog Apache License 2.0 UpdatedApr 16, 2020 -
riscv-dv Public
Forked from chipsalliance/riscv-dvSV/UVM based instruction generator for RISC-V processor verification
SystemVerilog Apache License 2.0 UpdatedApr 16, 2020 -
rv_plic Public
Forked from pulp-platform/rv_plicDevelopment Fork (unstable)
SystemVerilog Apache License 2.0 UpdatedApr 1, 2020 -
riscv-dbg Public
Forked from pulp-platform/riscv-dbgRISC-V Debug Support for our PULP Cores
SystemVerilog Other UpdatedApr 1, 2020 -
ariane-ethernet Public
Forked from lowRISC/ariane-ethernetopen-source Ethenet media access controller for Ariane on Genesys-2
SystemVerilog MIT License UpdatedApr 1, 2020 -
axi_slice Public
Forked from pulp-platform/axi_slicePipelines the AXI path with FIFOs
SystemVerilog Other UpdatedApr 1, 2020 -
axi Public
Forked from pulp-platform/axiAXI4 and AXI4-Lite interface definitions and testbench utilities
SystemVerilog Other UpdatedApr 1, 2020 -
common_cells Public
Forked from pulp-platform/common_cellsCommon SV components
SystemVerilog Other UpdatedApr 1, 2020 -
axi_node Public
Forked from pulp-platform/axi_nodeAXI X-Bar
SystemVerilog Other UpdatedApr 1, 2020 -
Cores-SweRV Public
Forked from chipsalliance/Cores-VeeR-EH1SweRV EH1 core
SystemVerilog Apache License 2.0 UpdatedFeb 27, 2020 -
opentitan Public
Forked from lowRISC/opentitanOpenTitan: Open source silicon root of trust
SystemVerilog Apache License 2.0 UpdatedFeb 27, 2020 -
fpu_div_sqrt_mvp Public
Forked from pulp-platform/fpu_div_sqrt_mvp[UNRELEASED] FP div/sqrt unit for transprecision
SystemVerilog Other UpdatedFeb 4, 2020 -
openpiton Public
Forked from PrincetonUniversity/openpitonThe OpenPiton Platform
Assembly UpdatedFeb 4, 2020
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