8000 dsidler (David Sidler) / Starred · GitHub
[go: up one dir, main page]
More Web Proxy on the site http://driver.im/
Skip to content
View dsidler's full-sized avatar
45 followers · 3 following

Achievements

Achievement: Pull SharkAchievement: Starstruckx3Achievement: Arctic Code Vault Contributor

Achievements

Achievement: Pull SharkAchievement: Starstruckx3Achievement: Arctic Code Vault Contributor

Block or report dsidler

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Stars

Showing results

minmit / tonic

A Programmable Hardware Architecture for Network Transport Logic

Verilog 35 13 Updated Oct 26, 2021

fpgasystems / doppiodb

doppioDB - A hardware accelerated database

C 49 18 Updated May 2, 2017

fpgasystems / dma-driver

SystemVerilog 21 8 Updated Dec 9, 2018

fpgasystems / fpga-network-stack

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

C++ 833 286 Updated Jul 2, 2025

OFS / opae-sdk

Open Programmable Acceleration Engine

C++ 265 89 Updated Jun 2, 2025

fpgasystems / Centaur

Centaur, a framework for hybrid CPU-FPGA databases

Verilog 27 11 Updated May 2, 2017

definelicht / hlslib

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

C++ 320 60 Updated Jan 20, 2025
0