8000 x86: Support vzeroupper instruction by BradleyWood · Pull Request #7788 · eclipse-omr/omr · GitHub
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x86: Support vzeroupper instruction #7788

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Merged
merged 1 commit into from
Jun 18, 2025
Merged

x86: Support vzeroupper instruction #7788

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25 changes: 15 additions & 10 deletions compiler/x/codegen/OMRInstOpCode.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -148,7 +148,7 @@ template <typename TBuffer> typename TBuffer::cursor_t OMR::X86::InstOpCode::OpC
}
else
{
TR::Instruction::VEX<3> vex(rex, modrm_opcode);
TR::Instruction::VEX<3> vex(rex);
vex.m = escape;
vex.L = enc;
vex.p = prefixes;
Expand Down Expand Up @@ -220,12 +220,14 @@ template <typename TBuffer> typename TBuffer::cursor_t OMR::X86::InstOpCode::OpC
}
// OpCode
buffer.append(opcode);
// ModRM
if (modrm_form)
{
buffer.append(TR::Instruction::ModRM(modrm_opcode));
}
}

// ModRM
if (modrm_form)
{
buffer.append(TR::Instruction::ModRM(modrm_opcode));
}

return buffer;
}

Expand All @@ -236,28 +238,31 @@ void OMR::X86::InstOpCode::OpCode_t::finalize(uint8_t* cursor) const
{
case 0xC4:
{
auto pVEX = (TR::Instruction::VEX<3>*)cursor;
auto pVEX = (TR::Instruction::VEX<3>*) cursor;
auto modRM = (TR::Instruction::ModRM*) (cursor + 4);
if (vex_v == VEX_vReg_)
{
pVEX->v = ~(modrm_form == ModRM_EXT_ ? pVEX->RM() : pVEX->Reg());
pVEX->v = ~(modrm_form == ModRM_EXT_ ? pVEX->RM(*modRM) : pVEX->Reg(*modRM));
}
}
break;
case 0xC5:
{
auto pVEX = (TR::Instruction::VEX<2>*)cursor;
auto modRM = (TR::Instruction::ModRM*) (cursor + 3);
if (vex_v == VEX_vReg_)
{
pVEX->v = ~(modrm_form == ModRM_EXT_ ? pVEX->RM() : pVEX->Reg());
pVEX->v = ~(modrm_form == ModRM_EXT_ ? pVEX->RM(*modRM) : pVEX->Reg(*modRM));
}
}
break;
case 0x62:
{
auto pVEX = (TR::Instruction::EVEX*)cursor;
auto modRM = (TR::Instruction::ModRM*) (cursor + 5);
if (vex_v == VEX_vReg_)
{
pVEX->v = ~(modrm_form == ModRM_EXT_ ? pVEX->RM() : pVEX->Reg());
pVEX->v = ~(modrm_form == ModRM_EXT_ ? pVEX->RM(*modRM) : pVEX->Reg(*modRM));
}
}
break;
Expand Down
25 changes: 10 additions & 15 deletions compiler/x/codegen/OMRInstruction.hpp
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Expand Up @@ -312,12 +312,10 @@ class OMR_EXTENSIBLE Instruction : public OMR::Instruction
uint8_t Z : 1; // P2[7] : z
// Byte 4: opcode
uint8_t opcode;
// Byte 5: ModRM
ModRM modrm;

inline EVEX() {}

inline EVEX(const REX& rex, uint8_t ModRMOpCode) : modrm(ModRMOpCode)
inline EVEX(const REX& rex, uint8_t ModRMOpCode)
{
escape = '\x62';
// reserved bits
Expand All @@ -330,6 +328,7 @@ class OMR_EXTENSIBLE Instruction : public OMR::Instruction
X = ~rex.X;
B = ~rex.B;

ModRM modrm(ModRMOpCode);
r = ~(rex.R & modrm.reg);

W = rex.W;
Expand All @@ -338,11 +337,11 @@ class OMR_EXTENSIBLE Instruction : public OMR::Instruction
a = 0;
}

inline uint8_t Reg() const
inline uint8_t Reg(const ModRM modrm) const
{
return modrm.Reg(~R);
}
inline uint8_t RM() const
inline uint8_t RM(const ModRM modrm) const
{
return modrm.RM(~B);
}
Expand All @@ -366,11 +365,9 @@ class OMR_EXTENSIBLE Instruction : public OMR::Instruction
uint8_t W : 1;
// Byte 3: opcode
uint8_t opcode;
// Byte 4: ModRM
ModRM modrm;

inline VEX() {}
inline VEX(const REX& rex, uint8_t ModRMOpCode) : modrm(ModRMOpCode)
inline VEX(const REX& rex)
{
escape = '\xC4';
R = ~rex.R;
Expand All @@ -383,11 +380,11 @@ class OMR_EXTENSIBLE Instruction : public OMR::Instruction
{
return X && B && !W && (m == 1);
}
inline uint8_t Reg() const
inline uint8_t Reg(const ModRM modrm) const
{
return modrm.Reg(~R);
}
inline uint8_t RM() const
inline uint8_t RM(const ModRM modrm) const
{
return modrm.RM(~B);
}
Expand All @@ -404,11 +401,9 @@ class OMR_EXTENSIBLE Instruction : public OMR::Instruction
uint8_t R : 1;
// Byte 2: opcode
uint8_t opcode;
// Byte 3: ModRM
ModRM modrm;

inline VEX() {}
inline VEX(const VEX<3>& other) : modrm(other.modrm)
inline VEX(const VEX<3>& other)
{
escape = '\xC5';
p = other.p;
Expand All @@ -417,11 +412,11 @@ class OMR_EXTENSIBLE Instruction : public OMR::Instruction
R = other.R;
opcode = other.opcode;
}
inline uint8_t Reg() const
inline uint8_t Reg(const ModRM modrm) const
{
return modrm.Reg(~R);
}
inline uint8_t RM() const
inline uint8_t RM(const ModRM modrm) const
{
return modrm.RM();
}
Expand Down
20 changes: 14 additions & 6 deletions compiler/x/codegen/OMRX86Instruction.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4510,23 +4510,31 @@ TR::Instruction* generateBreakOnDFSet(TR::CodeGenerator *cg, TR::Instruction* cu
}

TR::Instruction *
generateInstruction(TR::Instruction *prev, TR::InstOpCode::Mnemonic op, TR::CodeGenerator *cg)
generateInstruction(TR::Instruction *prev,
TR::InstOpCode::Mnemonic op,
TR::CodeGenerator *cg,
OMR::X86::Encoding encoding)
{
return new (cg->trHeapMemory()) TR::Instruction(op, prev, cg);
return new (cg->trHeapMemory()) TR::Instruction(op, prev, cg, encoding);
}

TR::Instruction *
generateInstruction(TR::InstOpCode::Mnemonic op, TR::Node * node, TR::CodeGenerator *cg)
generateInstruction(TR::InstOpCode::Mnemonic op,
TR::Node * node,
TR::CodeGenerator *cg,
OMR::X86::Encoding encoding)
{
return new (cg->trHeapMemory()) TR::Instruction(node, op, cg);
return new (cg->trHeapMemory()) TR::Instruction(node, op, cg, encoding);
}

TR::Instruction *
generateInstruction(TR::InstOpCode::Mnemonic op,
TR::Node * node,
TR::RegisterDependencyConditions *cond, TR::CodeGenerator *cg)
TR::RegisterDependencyConditions *cond,
TR::CodeGenerator *cg,
OMR::X86::Encoding encoding)
{
return new (cg->trHeapMemory()) TR::Instruction(cond, node, op, cg);
return new (cg->trHeapMemory()) TR::Instruction(cond, node, op, cg, encoding);
}

TR::X86MemInstruction *
Expand Down
6 changes: 3 additions & 3 deletions compiler/x/codegen/OMRX86Instruction.hpp
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Expand Up @@ -3307,9 +3307,9 @@ TR::X86RegRegInstruction * generateRegRegInstruction(TR::Instruction *, TR::Ins
*/
TR::Instruction * generateBreakOnDFSet(TR::CodeGenerator *cg, TR::Instruction* cursor = NULL);

TR::Instruction * generateInstruction(TR::InstOpCode::Mnemonic, TR::Node *, TR::RegisterDependencyConditions * cond, TR::CodeGenerator *cg);
TR::Instruction * generateInstruction(TR::InstOpCode::Mnemonic op, TR::Node * node, TR::CodeGenerator *cg);
TR::Instruction * generateInstruction(TR::Instruction *prev, TR::InstOpCode::Mnemonic op, TR::CodeGenerator *cg);
TR::Instruction * generateInstruction(TR::InstOpCode::Mnemonic, TR::Node *, TR::RegisterDependencyConditions * cond, TR::CodeGenerator *cg, OMR::X86::Encoding encoding = OMR::X86::Default);
TR::Instruction * generateInstruction(TR::InstOpCode::Mnemonic op, TR::Node * node, TR::CodeGenerator *cg, OMR::X86::Encoding encoding = OMR::X86::Default);
TR::Instruction * generateInstruction(TR::Instruction *prev, TR::InstOpCode::Mnemonic op, TR::CodeGenerator *cg, OMR::X86::Encoding encoding = OMR::X86::Default);

TR::X86ImmInstruction * generateImmInstruction(TR::InstOpCode::Mnemonic op, TR::Node * node, int32_t imm, TR::RegisterDependencyConditions * cond, TR::CodeGenerator *cg);
TR::X86ImmInstruction * generateImmInstruction(TR::InstOpCode::Mnemonic op, TR::Node * node, int32_t imm, TR::CodeGenerator *cg, int32_t reloKind=TR_NoRelocation);
Expand Down
5 changes: 5 additions & 0 deletions compiler/x/codegen/X86Ops.ins
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Expand Up @@ -6035,6 +6035,11 @@ INSTRUCTION(VFNMSUB231SDRegRegMem, vfnmsub231sd,
PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_DoubleFP | IA32OpProp_UsesTarget),
PROPERTY1(IA32OpProp1_XMMSource | IA32OpProp1_SourceIsMemRef | IA32OpProp1_XMMTarget),
FEATURES(0)),
INSTRUCTION(VZEROUPPER, vzeroupper,
BINARY(VEX_L128, VEX_vNONE, PREFIX___, REX__, ESCAPE_0F__, 0x77, 0, ModRM_NONE, Immediate_0),
PROPERTY0(IA32OpProp_ModifiesTarget),
PROPERTY1(IA32OpProp1_XMMTarget | IA32OpProp1_TargetRegIsImplicit | IA32OpProp1_XMMTarget),
FEATURES(X86FeatureProp_VEX128Supported | X86FeatureProp_VEX128RequiresAVX)),
INSTRUCTION(CLWBMem, clwb,
BINARY(VEX_L___, VEX_vNONE, PREFIX_66, REX__, ESCAPE_0F__, 0xae, 6, ModRM_RM__, Immediate_0),
PROPERTY0(0),
Expand Down
13 changes: 7 additions & 6 deletions fvtest/compilerunittest/x/BinaryEncoder.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -34,12 +34,12 @@ TR::RealRegister *getRealRegister(TR::RealRegister::RegNum regNum, TR::CodeGener
return rr;
}

class XDirectEncodingTest : public TRTest::BinaryEncoderTest<>, public ::testing::WithParamInterface<std::tuple<TR::InstOpCode::Mnemonic, TRTest::BinaryInstruction>> {};
class XDirectEncodingTest : public TRTest::BinaryEncoderTest<>, public ::testing::WithParamInterface<std::tuple<TR::InstOpCode::Mnemonic, OMR::X86::Encoding, TRTest::BinaryInstruction>> 88A8 {};

TEST_P(XDirectEncodingTest, encode) {
auto instr = generateInstruction(std::get<0>(GetParam()), fakeNode, cg());
TR::Instruction *instr = generateInstruction(std::get<0>(GetParam()), fakeNode, cg(), std::get<1>(GetParam()));

ASSERT_EQ(std::get<1>(GetParam()), encodeInstruction(instr));
ASSERT_EQ(std::get<2>(GetParam()), encodeInstruction(instr));
}

class XLabelEncodingTest : public TRTest::BinaryEncoderTest<>, public ::testing::WithParamInterface<std::tuple<TR::InstOpCode::Mnemonic, size_t, TRTest::BinaryInstruction>> {};
Expand Down Expand Up @@ -126,9 +126,10 @@ TEST_P(XRegMemEncodingTest, encode) {
}

INSTANTIATE_TEST_CASE_P(Special, XDirectEncodingTest, ::testing::Values(
std::make_tuple(TR::InstOpCode::UD2, "0f0b"),
std::make_tuple(TR::InstOpCode::INT3, "cc"),
std::make_tuple(TR::InstOpCode::RET, "c3")
std::make_tuple(TR::InstOpCode::UD2, OMR::X86::Default, "0f0b"),
std::make_tuple(TR::InstOpCode::INT3, OMR::X86::Default, "cc"),
std::make_tuple(TR::InstOpCode::RET, OMR::X86::Default, "c3"),
std::make_tuple(TR::InstOpCode::VZEROUPPER, OMR::X86::VEX_L128, "c5f877")
));

INSTANTIATE_TEST_CASE_P(Special, XLabelEncodingTest, ::testing::Values(
Expand Down
0