Simulation of a Cache with various ways to cache data.
The input to the cache simulator is a memory access trace, which we have generated by executing real programs. The trace contains memory addresses accessed during program execution. The cache simulator will have to use these addresses to determine if the access is a hit or a miss, and the actions to perform in each case. The memory trace file consists of multiple lines. Each line of the trace file corresponds to a memory accesses performed by the program. Each line consists of two columns, which are space separated. The second column reports 48-bit memory address that has been accessed by the program while the first column indicates whether the memory access is a read (R) or a write (W). The trace file always ends with a #eof string.
The program supports the following usage interface: ./first cache size block size cache policy associativity prefetch size trace file
where: A) is the total size of the cache in bytes. This number should be a power of 2. B) is a power of 2 integer that specifies the size of the cache block in bytes. C) Here is valid cache policy is fifo and lru if you do the extra credit. D) is one of: direct - simulate a direct mapped cache. assoc - simulate a fully associative cache. assoc:n - simulate an n way associative cache. n will be a power of 2. E) is the number of ajacent blocks that should be prefetched by the prefetcher in case of a miss F) is the name of the input trace file.