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Name		Name	Last commit message	Last commit date
Latest commit History 83 Commits
6_64_decoder_signals.psf		6_64_decoder_signals.psf
6_64_decoder_signals_extracted.psf		6_64_decoder_signals_extracted.psf
__MACOSX		__MACOSX
lab1_buffer		lab1_buffer
lab1_buffer_x4		lab1_buffer_x4
lab1_buffer_x4_80um		lab1_buffer_x4_80um
lab1_buffer_x4_80um_sim/schematic		lab1_buffer_x4_80um_sim/schematic
lab1_buffer_x4_sim/schematic		lab1_buffer_x4_sim/schematic
lab1_inv		lab1_inv
lab1_inv_x4		lab1_inv_x4
lab1sim/schematic		lab1sim/schematic
lab2_NORA		lab2_NORA
lab2_NORA_NAND		lab2_NORA_NAND
lab2_NORA_NAND_x1		lab2_NORA_NAND_x1
lab2_NORA_inv		lab2_NORA_inv
lab2_NORA_sim/schematic		lab2_NORA_sim/schematic
lab2_NORA_x1		lab2_NORA_x1
lab2_inv_sim/schematic		lab2_inv_sim/schematic
lab2_signal_gen		lab2_signal_gen
lab2and		lab2and
lab2decode_Y0/schematic		lab2decode_Y0/schematic
lab2decode_Y0_sim/schematic		lab2decode_Y0_sim/schematic
lab2decode_Y1/schematic		lab2decode_Y1/schematic
lab2decode_Y2/schematic		lab2decode_Y2/schematic
lab2decode_Y3/schematic		lab2decode_Y3/schematic
lab2decode_fullsim/schematic		lab2decode_fullsim/schematic
lab2decode_sim/schematic		lab2decode_sim/schematic
lab2decoder		lab2decoder
lab2decoder_sim/schematic		lab2decoder_sim/schematic
lab2decoder_v2		lab2decoder_v2
lab2decoder_v3		lab2decoder_v3
lab2decoder_v3_sim/schematic		lab2decoder_v3_sim/schematic
lab2inv_720_480		lab2inv_720_480
lab2inv_x4_mod		lab2inv_x4_mod
lab2inv_x5		lab2inv_x5
lab2inv_x7		lab2inv_x7
lab2nand		lab2nand
lab2nand_720_480		lab2nand_720_480
lab2nand_inv_sim/schematic		lab2nand_inv_sim/schematic
lab2nand_x2		lab2nand_x2
lab2states		lab2states
lab3_dff		lab3_dff
lab3_dff_casc/schematic		lab3_dff_casc/schematic
lab3_dff_casc_skew/schematic		lab3_dff_casc_skew/schematic
lab3_dff_v2		lab3_dff_v2
lab3_latch		lab3_latch
lab3_signal_gen		lab3_signal_gen
lab3_tb		lab3_tb
lab3states		lab3states
lab4_2_4decoder_en		lab4_2_4decoder_en
lab4_4_16decoder_en		lab4_4_16decoder_en
lab4_6_64decoder_en		lab4_6_64decoder_en
lab4_8_bitline_cond		lab4_8_bitline_cond
lab4_8_bitline_cond_bussed		lab4_8_bitline_cond_bussed
lab4_8_inv_bussed		lab4_8_inv_bussed
lab4_8_sense_amp		lab4_8_sense_amp
lab4_8_sense_amp_sigGen		lab4_8_sense_amp_sigGen
lab4_8_sense_amp_sim/schematic		lab4_8_sense_amp_sim/schematic
lab4_8_sram_word_gen		lab4_8_sram_word_gen
lab4_8_write_driver		lab4_8_write_driver
lab4_8_write_driver_bussed		lab4_8_write_driver_bussed
lab4_8_write_driver_sigGen		lab4_8_write_driver_sigGen
lab4_8_write_driver_sim/schematic		lab4_8_write_driver_sim/schematic
lab4_decoder_load_4		lab4_decoder_load_4
lab4_dff6		lab4_dff6
lab4_dff8		lab4_dff8
lab4_load16		lab4_load16
lab4_readmarg		lab4_readmarg
lab4_readmarg_2		lab4_readmarg_2
lab4_rowdecoder_signalgen		lab4_rowdecoder_signalgen
lab4_rowdecoder_tb		lab4_rowdecoder_tb
lab4_sense_amp_sigGen		lab4_sense_amp_sigGen
lab4_sense_amp_sim/schematic		lab4_sense_amp_sim/schematic
lab4_sense_ampl		lab4_sense_ampl
lab4_snm		lab4_snm
lab4_snm_2		lab4_snm_2
lab4_sram		lab4_sram
lab4_sram_array_test/schematic		lab4_sram_array_test/schematic
lab4_sram_cell		lab4_sram_cell
lab4_sram_cell_array_64x64		lab4_sram_cell_array_64x64
lab4_sram_cell_array_8x8		lab4_sram_cell_array_8x8
lab4_sram_cell_gen		lab4_sram_cell_gen
lab4_sram_cell_test		lab4_sram_cell_test
lab4_sram_test		lab4_sram_test
lab4_sram_test_gen		lab4_sram_test_gen
lab4_sram_word		lab4_sram_word
lab4_sram_word_scaling		lab4_sram_word_scaling
lab4_sram_word_test		lab4_sram_word_test
lab4_write_driver		lab4_write_driver
lab4_write_driver_sigGen		lab4_write_driver_sigGen
lab4_write_driver_sigGen_nandita		lab4_write_driver_sigGen_nandita
lab4_write_driver_sim/schematic		lab4_write_driver_sim/schematic
lab4_writemarg		lab4_writemarg
lab4_writemarg_2/schematic		lab4_writemarg_2/schematic
lab4proposal		lab4proposal
labs1-2		labs1-2
.oalib		.oalib
cdsinfo.tag		cdsinfo.tag
data.dm		data.dm
hi.txt		hi.txt

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