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RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.

Verilog 41 18 Updated Jan 10, 2024

The High-Frequency Trading FPGA System is an ultra-low latency platform for electronic trading on FPGAs. It features a TCP/IP stack, order matching engine, custom IP core, and risk management modul…

Verilog 105 25 Updated Apr 25, 2024

Opensource DDR3 Controller

Verilog 356 49 Updated Jun 14, 2025

10Gb Ethernet Switch

C 220 26 Updated Apr 25, 2025

A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器,用来读写硬盘。

SystemVerilog 105 36 Updated Sep 14, 2023

simple replacement for setpci/lspci and linear memory readout

C 12 1 Updated Mar 23, 2023

An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-sp…

Verilog 767 129 Updated Dec 6, 2024

parameterized AXIS FIFO design

Verilog 9 9 Updated Jul 18, 2017

The tool can install v2ray on the Doprax, including VMess and VLess protocols, it will automatically switch IP, you need to fork this projects, read readme.md and run it. Create By ifeng.

Dockerfile 8,393 22,628 Updated Apr 25, 2025
Verilog 5 Updated May 24, 2022

Simple program to read & write to a pci device from userspace

C 322 117 Updated Apr 7, 2019

在vscode上的数字设计开发插件

Verilog 380 23 Updated Jan 27, 2023

Hardware Assisted IEEE 1588 IP Core

Verilog 29 11 Updated Jul 17, 2014

A DDR3 memory controller in Verilog for various FPGAs

Verilog 484 97 Updated Oct 10, 2021

Verilog HDL UART Transmitter

Verilog 1 Updated Jun 16, 2019

Verilog HDL Cross Clock Domain Register

Verilog 3 1 Updated Jun 15, 2019

read process memory with process_vm_readv

C 16 5 Updated Feb 10, 2020

memory scanner for Linux

C 1 Updated Apr 6, 2020

Various process memory related utilities for Linux

C 7 Updated Mar 25, 2020

Memory cheat tool for Windows and Linux games

C 135 18 Updated Sep 16, 2016

simple header that helps for LD_PRELOAD tricks

C 4 Updated Jun 11, 2014

A collection of gdb tips. 100 maybe just mean many here.

Go 3,172 716 Updated Oct 30, 2023

VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs

Verilog 47 18 Updated Jan 19, 2021

Smbus VHDL (based on I2c) with PEC

VHDL 1 1 Updated Dec 19, 2020

An i2c master controller implemented in Verilog

Verilog 31 15 Updated Jul 26, 2017

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

SystemVerilog 1,315 300 Updated Jul 1, 2025

A Verilog implementation of DisplayPort protocol for FPGAs

Verilog 250 58 Updated Mar 15, 2019

An FPGA based GDROM emulator for the Sega Dreamcast

Verilog 156 37 Updated Feb 18, 2023

Change part number or package in a Xilinx 7-series FPGA bitstream

C 39 13 Updated Apr 27, 2020
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