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OpenVoice Public
Forked from myshell-ai/OpenVoiceInstant voice cloning by MyShell.
Python MIT License UpdatedMay 30, 2024 -
DIT_FFT Public
Forked from Pav1pk/DIT_FFTDecimation In Time, Design, Verification and Sythesis for OFDM Communications
Verilog UpdatedMay 27, 2024 -
Awesome-Chinese-LLM Public
Forked from HqWu-HITCS/Awesome-Chinese-LLM整理开源的中文大语言模型，以规模较小、可私有化部署、训练成本较低的模型为主，包括底座模型，垂直领域微调及应用，数据集与教程等。
2 UpdatedMay 19, 2024 -
basic_verilog Public
Forked from pConst/basic_verilogMust-have verilog systemverilog modules
Verilog UpdatedMay 16, 2024 -
OpenFPGA Public
Forked from lnis-uofu/OpenFPGAAn Open-source FPGA IP Generator
Verilog MIT License UpdatedApr 7, 2024 -
awesome-opensource-hardware Public
Forked from aolofsson/awesome-opensource-hardwareList of awesome open source hardware tools, generators, and reusable designs
Python MIT License UpdatedApr 5, 2024 -
chiselverify Public
Forked from chiselverify/chiselverifyA dynamic verification library for Chisel.
Scala BSD 2-Clause "Simplified" License UpdatedApr 3, 2024 -
sv2v Public
Forked from zachjs/sv2vSystemVerilog to Verilog conversion
Haskell BSD 3-Clause "New" or "Revised" License UpdatedMar 11, 2024 -
RISC-V-Processor-with-Pipelining Public
Forked from EngAhmed21/RISC-V-Processor-with-PipeliningImplementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and multi cycle instructions, ALU unit works in parallel with a mult…
Verilog UpdatedFeb 12, 2024 -
tnoc Public
Forked from taichi-ishitani/tnocNetwork on Chip Implementation written in SytemVerilog
SystemVerilog Apache License 2.0 UpdatedAug 27, 2022 -
jksb-sysu Public
Forked from Aoi-cn/jksb-sysu中山大学健康申报自动化（Github Actions）
Python GNU General Public License v3.0 UpdatedAug 10, 2022 -
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gdsiistl Public
Forked from dteal/gdsiistlConverts GDSII files to STL files.
Python GNU General Public License v3.0 UpdatedApr 22, 2020 -
FPGA-SM3-HASH Public
Forked from raymondrc/FPGA-SM3-HASHDescription of Chinese SM3 Hash algorithm with Verilog HDL
Verilog MIT License UpdatedAug 5, 2018 -
lr_riscv_cpu Public
Forked from camelop/lr_riscv_cpu2017 SJTU SYSTEM project (RISCV-CPU with base inst)
Verilog UpdatedJul 30, 2018 -
verilog_fixed_point_math_library Public
Forked from freecores/verilog_fixed_point_math_libraryFixed Point Math Library for Verilog
Verilog GNU Lesser General Public License v2.1 UpdatedJul 17, 2014
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