Stars
AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).
Verilog AXI components for FPGA implementation
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
Verification IP for APB protocol
SystemVerilog VIP for AMBA APB protocol
UVM register utility generation by inputting xls table
UVM APB VIP, part of AMBA3&AMBA4 feature supported
Random instruction generator for RISC-V processor verification
An Open-Source Design and Verification Environment for RISC-V
4 stage, in-order, compute RISC-V core based on the CV32E40P
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Functional verification project for the CORE-V family of RISC-V cores.
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
hfyfpga / tinyriscv
Forked from liangkangnan/tinyriscvA very simple and easy to understand RISC-V core.
IC design and development should be faster，simpler and more reliable