GitHub - hppRC/csjikken2-2: simple CPU written in Verilog HDL

Name		Name	Last commit message	Last commit date
Latest commit History 20 Commits
bin2v		bin2v
image		image
mips_de2-115		mips_de2-115
.gitignore		.gitignore
bin2v.tar.gz		bin2v.tar.gz
cadsetup.bash.altera		cadsetup.bash.altera
cpu.v		cpu.v
mips_de2-115.tar.gz		mips_de2-115.tar.gz
motor.bin		motor.bin
motor.c		motor.c
motor.o		motor.o
motor.s		motor.s
mult.c		mult.c
my_print.bin		my_print.bin
my_print.c		my_print.c
my_print.o		my_print.o
my_print.s		my_print.s
my_print_B_while.bin		my_print_B_while.bin
my_print_B_while.c		my_print_B_while.c
my_print_B_while.o		my_print_B_while.o
my_print_B_while.s		my_print_B_while.s
my_scan.bin		my_scan.bin
my_scan.c		my_scan.c
my_scan.o		my_scan.o
my_scan.s		my_scan.s
print_B.bin		print_B.bin
print_B_while.bin		print_B_while.bin
print_all_char.bin		print_all_char.bin
print_all_char.c		print_all_char.c
print_all_char.o		print_all_char.o
print_all_char.s		print_all_char.s
rom8x1024_DE2.mif		rom8x1024_DE2.mif
rom8x1024_sim.v		rom8x1024_sim.v
sosuu.bin		sosuu.bin
sosuu.c		sosuu.c
sosuu.o		sosuu.o
sosuu.s		sosuu.s