Tags: hqkang/hdl
Tags
kc705,common: Mem_interconnect maximize performance For FMCOMMS1, when both the ADC and DAC DMAs are active, the system was unstable. With this fix, it the system seems to be stable.
Added phys_opt_design step for fixing timing The FMCOMMS1 meets timing on ZED/ZC702 only if the phys_opt_design step is part of the implmentation flow, with the Explore argument. "This step performs physical optimizations such as timing-driven replicaiton of high fanouts nets to improve timing results"