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openwifi-hw Public
Forked from open-sdr/openwifi-hwopen-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
Verilog GNU Affero General Public License v3.0 UpdatedMay 31, 2022 -
verilog-axis Public
Forked from alexforencich/verilog-axisVerilog AXI stream components for FPGA implementation
Python MIT License UpdatedOct 17, 2021 -
verilog-axi Public
Forked from alexforencich/verilog-axiVerilog AXI components for FPGA implementation
Verilog MIT License UpdatedOct 12, 2021 -
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SatCommSystem-QPSK-OFDM-LSEstimation-TransionosphericChannel Public
Forked from fosfor15/SatCommSystem-QPSK-OFDM-LSEstimation-TransionosphericChannelMATLAB Imitation Modeling for the BER of the Satellite Communication System using QPSK and OFDM Modulation with LS Channel Estimation based on Pilot Signals in the Transionospheric Communication Ch…
MATLAB MIT License UpdatedJul 24, 2020 -
hdl Public
Forked from analogdevicesinc/hdlHDL libraries and projects
Verilog Other UpdatedJul 23, 2020 -
corundum Public
Forked from corundum/corundumOpen source, high performance, FPGA-based NIC
Verilog Other UpdatedApr 1, 2020 -
digital-fm-stereo-modulator Public
Forked from diocorreia/digital-fm-stereo-modulatorAll-digital FM Stereo Modulator described in Verilog.
Verilog UpdatedMar 31, 2020 -
DSP-RTL-Lib Public
Forked from ahmedshahein/DSP-RTL-LibRTL Verilog library for various DSP modules
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Digital-Hardware-Modelling Public
Forked from varunnagpaal/Digital-Hardware-ModellingDigital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
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verilog-ethernet Public
Forked from alexforencich/verilog-ethernetVerilog Ethernet components for FPGA implementation
Verilog MIT License UpdatedFeb 4, 2020 -
PoC Public
Forked from VLSI-EDA/PoCIP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
VHDL Other UpdatedJan 13, 2020 -
openwifi Public
Forked from open-sdr/openwifiopen-source Wi-Fi baseband chip/FPGA design
C GNU Affero General Public License v3.0 UpdatedDec 13, 2019 -
5g-nr-pusch Public
Forked from gc1905/5g-nr-puschMATLAB implementation of a transmitter and receiver chain of the 5G NR Physical Uplink Shared Channel (PUSCH) defined by 3GPP rel 15.
MATLAB BSD 2-Clause "Simplified" License UpdatedNov 24, 2019 -
free-programming-books-zh_CN Public
Forked from justjavac/free-programming-books-zh_CN📚 免费的计算机编程类中文书籍，欢迎投稿
GNU General Public License v3.0 UpdatedNov 24, 2019 -
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DeepLearning-500-questions Public
Forked from scutan90/DeepLearning-500-questions深度学习500问，以问答形式对常用的概率知识、线性代数、机器学习、深度学习、计算机视觉等热点问题进行阐述，以帮助自己及有需要的读者。 全书分为17个章节，20多万字。由于水平有限，书中不妥之处恳请广大读者批评指正。 未完待续............ 如有意合作，联系scutjy2015@163.com 版权所有，违权必究 Tan 2018.06
TeX GNU General Public License v3.0 UpdatedNov 14, 2018 -
pp4fpgas-cn Public
Forked from xupsh/pp4fpgas-cn中文版 Parallel Programming for FPGAs
CSS UpdatedOct 29, 2018 -
pp4fpgas Public
Forked from KastnerRG/pp4fpgasParallel Programming for FPGAs -- An open-source high-level synthesis book
TeX UpdatedOct 26, 2018 -
aws-fpga-app-notes Public
Forked from awslabs/aws-fpga-app-notesApplication notes for the F1 EC2 Instance
C++ Other UpdatedOct 5, 2018 -
fpga-partial-reconfig Public
Forked from intel/fpga-partial-reconfigTutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
SystemVerilog MIT License UpdatedOct 5, 2018 -
RTL, Cmodel, and testbench for NVDLA
Verilog Other UpdatedSep 20, 2018 -
Xilinx-OpenHW-Contest Public
Forked from louisliuwei/Xilinx-OpenHW-ContestXilinx OpenHW Contest Source Code
Verilog UpdatedSep 17, 2018 -
HLx_Examples Public
Forked from weshu/HLx_ExamplesOpen Source HLx Examples
MATLAB BSD 3-Clause "New" or "Revised" License UpdatedAug 27, 2018 -
ofdm_ieee80211a Public
Forked from yuhao127jl/ofdm_ieee80211aOFDM baseband processing systerm based on IEEE 802.11a
MATLAB UpdatedJul 26, 2018 -
Viterbi-Decoder-in-Verilog Public
Forked from jfoshea/Viterbi-Decoder-in-VerilogAn efficient implementation of the Viterbi decoding algorithm in Verilog
Verilog UpdatedJul 3, 2018 -
verilog-lfsr Public
Forked from alexforencich/verilog-lfsrFully parametrizable combinatorial parallel LFSR/CRC module
Verilog MIT License UpdatedJun 14, 2018 -
verilog Public
Forked from seldridge/verilogRepository for basic (and not so basic) Verilog blocks with high re-use potential
Verilog Apache License 2.0 UpdatedMar 15, 2018
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