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Add <code>@protected</code> onto <code>execute</code> on <code>Conditional</code>s

#596

· mkorbel1 opened

on Jun 10, 2025

Warn when <code>Simulator</code> runs but no events have been registered

#595

· mkorbel1 opened

on Jun 10, 2025

Generation of <code>struct</code>s and <code>enum</code>s in output SystemVerilog

#594

· mkorbel1 opened

on May 22, 2025

Enable Const() to use an Enum as an argument, and name it appropriately

#592

· desmonddak opened

on Apr 16, 2025

LogicValue radixString code should allow for prefix-free strings

#591

· desmonddak opened

on Mar 26, 2025

Prune unused, unnamed module outputs when generating SV

#590

· mkorbel1 opened

on Mar 20, 2025

Make it easier to flop <code>LogicArray</code>s and <code>LogicStructure</code>s

#587

· mkorbel1 opened

on Mar 11, 2025

Capability to disable timestamp in output verilog

#579

· awmoore-intel opened

on Mar 5, 2025

LogicStructure Example in User Guide doesn't compile

good first issue

#578

· awmoore-intel opened

on Mar 5, 2025

Add documentation to User Guide for automations like flop, cases, mux, etc.

#577

· awmoore-intel opened

on Mar 5, 2025

WaveDumper outputs empty file when test() {expect()} fails

#574

· awmoore-intel opened

on Feb 26, 2025

Add <code>State.ssa</code> to enable SSA in <code>FiniteStateMachine</code>

#571

· mkorbel1 opened

on Feb 25, 2025

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