8000 ironsteel (Rangel Ivanov) / Starred · GitHub
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Rust 1 Updated Jun 7, 2025

Some experiments I did with the Raspberry Pi Pico

C++ 224 32 Updated May 8, 2024

Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)

Starlark 1 Updated May 13, 2025

A Turbo circuit with a MHz display that can slow down the CPU speed

C++ 41 4 Updated May 31, 2025

Repurposing existing HDL tools to help writing better code

Python 213 26 Updated Jun 6, 2024

VHDL Native Synthesizable Library

VHDL 10 1 Updated Jun 6, 2025

MIPI testing with LiteX on CrossLink-NX

Python 13 2 Updated Mar 10, 2021

A GPU acceleration flow for RTL simulation with batch stimulus

C++ 112 8 Updated Apr 1, 2024

LiteX-based gateware for LimeSDR boards.

VHDL 14 7 Updated Jun 18, 2025

Native32 reverse engineering and emulation project

Python 8 1 Updated Jun 1, 2025
Verilog 3 Updated May 8, 2025

Optimized library for driving parallel eink displays with the ESP32

C++ 86 8 Updated Jul 2, 2025

A port of Mbed-TLS for the Classic Macintosh OS 7/8/9

C 58 3 Updated Apr 11, 2025

W65C832 (32 bit 6502) in an FPGA.

Verilog 22 1 Updated Jun 22, 2025

RealtimeIO for LinuxCNC based on an FPGA

Python 79 18 Updated Sep 2, 2024

riocore

Python 51 14 Updated Jul 8, 2025

SDK sch&layout reference design and datasheet documention

C 62 16 Updated Feb 1, 2024

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

VHDL 1,802 271 Updated Jul 7, 2025

This repository contains high-resolution photos documenting the restoration of a 1979 Apple ][+, with serial number A2S2-522915.

2 Updated Feb 27, 2025

Xilinx Unisim Library in Verilog

Verilog 78 25 Updated Jul 22, 2020

This repository contains high-resolution photos documenting the restoration of a 1977 original Apple ][, with serial number A2S1-28243.

2 Updated Feb 21, 2025

SLogic_Combo8

C 5 Updated Feb 6, 2025

An FPGA reverse engineering and documentation project

Rust 2 Updated Feb 23, 2025

Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)

Starlark 133 55 Updated Jun 14, 2025

Fast realtime softare rendering library for C++14 using SSE/AVX/NEON. 2D, 3D and isometric rendering with minimal system dependencies.

C++ 98 7 Updated Jul 6, 2025

End-to-end synthesis and P&R toolchain

Rust 85 6 Updated Jul 8, 2025

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

SystemVerilog 94 5 Updated Jun 13, 2025

SW and HW accelerated GPU driver for Windows 9x Virtual Machines

C 901 29 Updated Jun 30, 2025

Easily manage your IoT device fleet with Edgehog at once. Get information on device status, deploy updates, geolocate your devices and much more!

Elixir 41 22 Updated Jun 6, 2025

Build a SDR SW/MW/LW Receiver with a Raspberry Pi Pico

C 378 58 Updated Jul 3, 2025
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