Tags: john-chidrupaya/VHDL_IP-Cores
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[TASK] Set ipcore versions to 1.0.0 Change-Id: I19a0a8da6455682b12dac1d2974afec5985fa754 Reviewed-on: http://brateggevoat1/gerrit/1785 Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at> Reviewed-by: Thomas Mair <thomas.mair@br-automation.com> Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[TASK] Revise simulation scripts * Add generic list forwarding from scripts to vhdl * Omit debug info (puts, echo, ..) * Move wave conversion to individual script Change-Id: I3436592fab471b4bb79a9a8fd877510c9c364b4f Reviewed-on: http://brateggevoat1/gerrit/1051 Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at> Reviewed-by: Thomas Mair <thomas.mair@br-automation.com> Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] HOSTIF: Dynamic buffer address write works with 16 bit host int… …erface This fix enables writing to the dynamic buffer address registers with 16 bit host interface. This commit adds byteenable signals between the host and the register file storing the base addresses for the MMU logic. Change-Id: I44c59d39154c2d493358ba33b9a17413b8cb76b8
[FEATURE] HOSTIF: Add asynchronous (de-)multiplexed parallel interface The asynchronous parallel host interface supports two modes: * Multiplexed address-/data-bus * Demultiplexed (separated) address-/data-bus The timing constraints for the host interface is automatically add to the Quartus project. Note that the port naming is not bounded to the timing constraints. Change-Id: I65f4b261c895df10efc1b83bc1df51a9eed3b1ca
[FIX] Second compare timer is only enabled with openMAC only and PDI
[TASK] X: remove ipcore revision from component files
[FEATURE] add host interface with Altera Avalon support
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