GitHub - kabeer11000/riscv: RISCV PC emulator. This repository contains a RISC-V CPU emulator designed to simulate hardware and execute RISC-V instructions. The project is open to contributions and research, with a focus on enabling WebAssembly (Wasm) support through Emscripten for browser integration.

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RISCV PC emulator. This repository contains a RISC-V CPU emulator designed to simulate hardware and execute RISC-V instructions. The project is open to contributions and research, with a focus on enabling WebAssembly (Wasm) support through Emscripten for browser integration.

GPL-3.0 license

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RISC-V CPU Emulator with WebAssembly Support

This repository contains a RISC-V CPU emulator designed to simulate hardware and execute RISC-V instructions. The project is open to contributions and research, with a focus on enabling WebAssembly (Wasm) support through Emscripten for browser integration. The emulator provides a flexible and extensible platform for experimenting with RISC-V architectures and exploring hardware emulation concepts.

Features:
- RISC-V CPU Emulation: Implements a basic RISC-V CPU with support for a subset of the RISC-V instruction set.
- WebAssembly Support: Compiles to WebAssembly using Emscripten, enabling integration into web browsers.
- Extensible Design: Modular architecture for easy extension and experimentation.
- Memory Management: Simulates memory with bounds checking and dynamic resizing.
- System Calls: Supports basic system calls (e.g., exit, write) for program interaction.
- Open for Research: Encourages contributions and research in hardware emulation and RISC-V architectures.

Getting Started:
1. Clone the repository:
git clone https://github.com/kabeer11000/riscv.git
cd riscv

Repository Structure:
- src/: Source code for the RISC-V emulator
- build/: Build directory (generated)
- examples/: Example RISC-V binaries for testing
- docs/: Documentation and technical details
- CMakeLists.txt: CMake build configuration
- LICENSE: License file
- README.md: This file

Usage:
The emulator can execute RISC-V binaries by loading them into memory and simulating the CPU's fetch-decode-execute cycle. Example usage:
RISCVCpu cpu;
cpu.load_program(program, 0x00000000); // Load program at memory address 0
cpu.run(); // Start emulation

Supported Instructions:
- R-type: ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND
- I-type: ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, LB, LH, LW, LBU, LHU, JALR
- S-type: SB, SH, SW
- B-type: BEQ, BNE, BLT, BGE, BLTU, BGEU
- U-type: LUI, AUIPC
- J-type: JAL
- System: ECALL, EBREAK

Contributing:
We welcome contributions! If you'd like to contribute, please:
1. Fork the repository.
2. Create a new branch for your feature or bug fix.
3. Submit a pull request with a detailed description of your changes.

License:
This project is licensed under the MIT License. See the LICENSE file for details.

Acknowledgments:
- Inspired by the RISC-V architecture and open-source emulation projects.

Contact:
For questions or feedback, please open an issue in the repository or contact [kabeer11000@gmail.com].

This project aims to bridge the gap between hardware emulation and web-based applications, providing a platform for education, research, and experimentation. Contributions and ideas are always welcome!