RISC-V is a RISC-based open instruction set architecture. The basic 32-bit integer instruction set in RISC-V is defined as RV32I. We are developing an optimized RV32I processor named RVCoreP, adopting five-stage pipelining targetting both FPGAs and ASICs. This project aims to evaluate our preliminary processor design regarding operating frequency and power consumption.
-
Notifications
You must be signed in to change notification settings - Fork 0
RISC-V Processor
License
kisek/rvcore_chip2
Folders and files
| Name | Name | Last commit message | Last commit date | |
|---|---|---|---|---|
Repository files navigation
About
RISC-V Processor
Topics
Resources
License
Stars
Watchers
Forks
Releases
No releases published
Packages 0
No packages published