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2022_r2_p1

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hdl: Zed-AD7768: Wideband fixed bug_2022_R2 (analogdevicesinc#1282)

* hdl: Zed-AD7768: Wideband fixed bug

In SPI control mode, when not used as GPIO the FILTER pin and when a crystal
is used as the clock source, this pin must be set to 1.
The START pin must be tied to a logic 1 through a pull-up resistor, when
it is not used.

Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>

2022_R2

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axi_ad7606x: Add the correct IP's name

Signed-off-by: Alin-Tudor Sferle <Alin-Tudor.Sferle@analog.com>
(cherry picked from commit 03c4276)

2021_R2

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Changed the default AD9081 profile for VCK190

* RX_mode=27, L=4, M=4, S=2, NP=12, Lane_rate=12.375 GHz
* TX_mode=23, L=4, M=4, S=2, NP=12, Lane_rate=12.375 GHz
* Ref_clk=375 MHz, Device_clk=125 MHz

add_ad4858_fmcz_zcu102

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ad4858_fmcz: add support for zcu102

The LVDS interface requires digital(delay) tuning by software.

2021_r1

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util_do_ram: Fix Rx path for interrupted transfers

When capture length is not programmed the DMA will interrupt the
transfer once it received all the samples he was set in its descriptor,
this case must be handled by resetting the read process and returning
an end of transfer (eot) to the data offload control logic.

2019_r2

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pluto: Fix dunf connection

usdrx1_legacy

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USDRX1 ulstrasound hdl reference design

legacy_fmcomms7

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FMCOMMS7 hdl reference design

legacy_fmcjesdadc1_zcu102

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FMCJESDADC1 hdl reference design for ZCU102 carrier

legacy_fmcjesdadc1_a10soc

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FMCJESDADC1 hdl reference design for A10SOC carrier
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