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Latex code for making neural networks diagrams
西北工业大学本科毕业设计论文模版 | Thesis Template for Northwestern Polytechnical University
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.
Formal verification tools for Chisel and RISC-V
Verilator open-source SystemVerilog simulator and lint system
Main repository for Deep Metric Learning via Lifted Structured Feature Embedding
Official release of InternLM series (InternLM, InternLM2, InternLM2.5, InternLM3).
LMDeploy is a toolkit for compressing, deploying, and serving LLMs.
基于 MaaFramework 与 Qt6 的物华弥新一键长草小助手 | 通用 MAA PC 端极速预备中！