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riscv-isa-manual Public
Forked from riscv/riscv-isa-manualRISC-V Instruction Set Manual
TeX Creative Commons Attribution 4.0 International UpdatedOct 17, 2024 -
riscv-v-spec Public
Forked from riscvarchive/riscv-v-specWorking draft of the proposed RISC-V V vector extension
Assembly Creative Commons Attribution 4.0 International UpdatedOct 17, 2024 -
axi Public
Forked from pulp-platform/axiAXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
SystemVerilog Other UpdatedOct 17, 2024 -
cva6 Public
Forked from openhwgroup/cva6The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Assembly Other UpdatedOct 17, 2024 -
ara2 Public
Forked from pulp-platform/araThe PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
C Other UpdatedOct 17, 2024 -
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openc910 Public
Forked from XUANTIE-RV/openc910OpenXuantie - OpenC910 Core
Verilog Apache License 2.0 UpdatedJul 30, 2024 -
riscv-matrix-extension-spec Public
Forked from XUANTIE-RV/riscv-matrix-extension-specA matrix extension proposal for AI applications under RISC-V architecture
TeX Apache License 2.0 UpdatedJul 30, 2024 -
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vroom Public
Forked from MoonbaseOtago/vroomVRoom! RISC-V CPU
Verilog GNU General Public License v3.0 UpdatedJul 28, 2023 -
OpenVectorInterface Public
Forked from semidynamics/OpenVectorInterfaceHome of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit
Other UpdatedDec 23, 2021
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