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VHDL library of high abstraction level synthesizable mathematical functions for multiplication, division and sin/cos functionalities and abc to dq transforms.
A workshop on Linux containers: Rebuild Docker from Scratch
Scripts to build and use docker images including GHDL
FUSE driver to read/write Windows' BitLocker-ed volumes under Linux / Mac OSX
SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improv…
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
MicroPython - a lean and efficient Python implementation for microcontrollers and constrained systems
😎 Awesome lists about all kinds of interesting topics
A package for Sublime Text that aids coding in the VHDL language.
VUnit is a unit testing framework for VHDL/SystemVerilog
🌊 Digital timing diagram rendering engine