Set PortCountersXmitWaitSupported flag #1
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PROBLEM: It is not possible to test PortXmitWait counter with ibsim. opensm ignores this counter because PortCountersXmitWaitSupported is not set SOLUTION: Set the flag PortCountersXmitWaitSupported in the Performance Management ClassPortInfo:CapabilityMask TESTS: 1. start IBSIM ➜ ibsim git:(master) ✗ ./ibsim/ibsim -s /home/cyrille/code/infiniband/topologies/test.ibsim 2. start OPENSM ➜ opensm git:(master) ✗ LD_PRELOAD=/home/cyrille/code/infiniband/ibsim/umad2sim/libumad2sim.so LD_LIBRARY_PATH=/home/cyrille/code/infiniband/opensm/opensm/.libs/:/home/cyrille/code/infiniband/opensm/complib/.libs:/home/cyrille/code/infiniband/opensm/libvendor/.libs ./opensm -f stdout 3. set XMIT_WAIT value in ibsim: sim> PerformanceSet "S-0002c90200405150"[1] PortCounters.PortXmitWait=123 S-0002c90200405150[1] PortCounters.PortXmitWait has been set to 123 4. run PERQUERY BEFORE modification in ibsim ➜ opensm git:(master) ✗ LD_PRELOAD=/home/cyrille/code/infiniband/ibsim/umad2sim/libumad2sim.so perfquery 5 1 PortSelect:......................1 CounterSelect:...................0x0000 SymbolErrorCounter:..............0 LinkErrorRecoveryCounter:........0 LinkDownedCounter:...............0 PortRcvErrors:...................0 PortRcvRemotePhysicalErrors:.....0 PortRcvSwitchRelayErrors:........0 PortXmitDiscards:................0 PortXmitConstraintErrors:........0 PortRcvConstraintErrors:.........0 CounterSelect2:..................0x00 LocalLinkIntegrityErrors:........0 ExcessiveBufferOverrunErrors:....0 VL15Dropped:.....................0 PortXmitData:....................720 PortRcvData:.....................720 PortXmitPkts:....................10 PortRcvPkts:.....................10 AFTER modification in ibsim PortSelect:......................1 CounterSelect:...................0x0000 SymbolErrorCounter:..............0 LinkErrorRecoveryCounter:........0 LinkDownedCounter:...............0 PortRcvErrors:...................0 PortRcvRemotePhysicalErrors:.....0 PortRcvSwitchRelayErrors:........0 PortXmitDiscards:................0 PortXmitConstraintErrors:........0 PortRcvConstraintErrors:.........0 CounterSelect2:..................0x00 LocalLinkIntegrityErrors:........0 ExcessiveBufferOverrunErrors:....0 VL15Dropped:.....................0 PortXmitData:....................720 PortRcvData:.....................720 PortXmitPkts:....................10 PortRcvPkts:.....................10 PortXmitWait:....................123 Signed-off-by: Cyrille Verrier <cyrille.verrier@fabriscale.com>
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==11780== 4 errors in context 1 of 1: ==11780== Syscall param write(buf) points to uninitialised byte(s) ==11780== at 0x5349F34: write (in /usr/lib64/libc-2.27.so) ==11780== by 0x40CA7E: send_trap (sim_mad.c:2014) ==11780== by 0x407D57: do_portinfo (sim_mad.c:672) ==11780== by 0x40C2CD: process_packet (sim_mad.c:1887) ==11780== by 0x41254B: sim_read_pkt (ibsim.c:484) ==11780== by 0x412D49: sim_run (ibsim.c:601) ==11780== by 0x4135B3: main (ibsim.c:783) ==11780== Address 0x1ffeffed44 is on thread 1's stack ==11780== in frame #1, created by send_trap (sim_mad.c:1971) ==11780== Uninitialised value was created by a stack allocation ==11780== at 0x40C832: send_trap (sim_mad.c:1971) Signed-off-by: Honggang Li <honli@redhat.com> Signed-off-by: Hal Rosenstock <hal@mellanox.com>
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PROBLEM:
It is not possible to test PortXmitWait counter with ibsim.
opensm ignores this counter because PortCountersXmitWaitSupported is not set
SOLUTION:
Set the flag PortCountersXmitWaitSupported in the Performance Management ClassPortInfo:CapabilityMask
TESTS:
start IBSIM
➜ ibsim git:(master) ✗ ./ibsim/ibsim -s /home/cyrille/code/infiniband/topologies/test.ibsim
start OPENSM
➜ opensm git:(master) ✗ LD_PRELOAD=/home/cyrille/code/infiniband/ibsim/umad2sim/libumad2sim.so LD_LIBRARY_PATH=/home/cyrille/code/infiniband/opensm/opensm/.libs/:/home/cyrille/code/infiniband/opensm/complib/.libs:/home/cyrille/code/infiniband/opensm/libvendor/.libs ./opensm -f stdout
set XMIT_WAIT value in ibsim:
sim> PerformanceSet "S-0002c90200405150"[1] PortCounters.PortXmitWait=123
S-0002c90200405150[1] PortCounters.PortXmitWait has been set to 123
run PERQUERY
BEFORE modification in ibsim
➜ opensm git:(master) ✗ LD_PRELOAD=/home/cyrille/code/infiniband/ibsim/umad2sim/libumad2sim.so perfquery 5 1
PortSelect:......................1
CounterSelect:...................0x0000
SymbolErrorCounter:..............0
LinkErrorRecoveryCounter:........0
LinkDownedCounter:...............0
PortRcvErrors:...................0
PortRcvRemotePhysicalErrors:.....0
PortRcvSwitchRelayErrors:........0
PortXmitDiscards:................0
PortXmitConstraintErrors:........0
PortRcvConstraintErrors:.........0
CounterSelect2:..................0x00
LocalLinkIntegrityErrors:........0
ExcessiveBufferOverrunErrors:....0
VL15Dropped:.....................0
PortXmitData:....................720
PortRcvData:.....................720
PortXmitPkts:....................10
PortRcvPkts:.....................10
AFTER modification in ibsim
PortSelect:......................1
CounterSelect:...................0x0000
SymbolErrorCounter:..............0
LinkErrorRecoveryCounter:........0
LinkDownedCounter:...............0
PortRcvErrors:...................0
PortRcvRemotePhysicalErrors:.....0
PortRcvSwitchRelayErrors:........0
PortXmitDiscards:................0
PortXmitConstraintErrors:........0
PortRcvConstraintErrors:.........0
CounterSelect2:..................0x00
LocalLinkIntegrityErrors:........0
ExcessiveBufferOverrunErrors:....0
VL15Dropped:.....................0
PortXmitData:....................720
PortRcvData:.....................720
PortXmitPkts:....................10
PortRcvPkts:.....................10
PortXmitWait:....................123
Signed-off-by: Cyrille Verrier cyrille.verrier@fabriscale.com