This repository contains examples, benchmarks and tests for the Coriolis VLSI toolchain and its older counterpart Alliance.
It contains all kinds of designs using Coriolis for p 8000 hysical design (typically placement and routing).
For any question, you may contact the team on Matrix.
You should clone the repository in ~/coriolis-2.x/src/, and install Coriolis and Alliance.
# Clone the repositories
mkdir -p ~/coriolis-2.x/src/
git clone https://github.com/lip6/coriolis.git
git clone https://github.com/lip6/alliance.git
git clone https://github.com/lip6/alliance-check-toolkit.git
# Install Alliance and Coriolis
cd coriolis
git submodule update --init
make -f Makefile.LIP6 install install_alliance
make -f Makefile.LIP6 install_docsAs an example, you can look at the Arlet6502 design in benchs/arlet6502/cmos. It uses pydoit to define build steps in dodo.py.
You can build it with:
./bin/crlenv bash
cd benchs/arlet6502/cmos
# Cleaning step
doit clean_flow
# Run each step individually
doit yosys
doit pnr
# You can just run this one, as it depends on the others
crlenv doit lvxIt's often nicer to use the viewer and see your design:
doit cgt
# Go to Tools->Python Script
# Write "doDesign"
# Enjoy