Stars
Generates Makefiles to synthesize, place, and route verilog using Vivado
A collection of resources on FPGA devices and development in general
Package manager and build abstraction tool for FPGA/ASIC development
Chisel: A Modern Hardware Design Language
Open deep learning compiler stack for cpu, gpu and specialized accelerators
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Flexible Intermediate Representation for RTL
HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs
Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
Fixed Point Math Library for Verilog
CMake template for Verilog and VHDL project and Altera/Xilinx FPGA target
Parallel Programming for FPGAs -- An open-source high-level synthesis book
collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning
Repository for basic (and not so basic) Verilog blocks with high re-use potential
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit