Stars
A DDR3 memory controller in Verilog for various FPGAs
Chinese Translation on <PCI Express Technology Comprehensive Guide to Generations 1.x, 2.x and 3.0> by Mindshare Mindshare
AMBA bus generator including AXI4, AXI3, AHB, and APB
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
An abstraction library for interfacing EDA tools
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Synthesizable and Parameterized Cache Controller in Verilog
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
Code for the paper "Interpretable Complex-Valued Neural Network"
Deep learning library for solving differential equations on top of PyTorch.
A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.
HDLBits website practices & solutions
Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-IV board.
FPGA implementation of Chinese SM4 encryption algorithm.
Description of Chinese SM3 Hash algorithm with Verilog HDL
A implement of Chinese SHA(SM3) on FPGA from SHU ACTION team