8000 [FIRRTL] Useless wire names could be useful as debug information · Issue #5360 · llvm/circt · GitHub
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[FIRRTL] Useless wire names could be useful as debug information #5360
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@uenoku

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@uenoku

#5288 changed DropName pass to literally drop useless names (mostly created as Chisel temporaries) by default for better verilog output but these names were previously used for error messages. For example, ExpandWhen is not able to produce good messages for wires created as Chisel temporary.

circuit Foo :
  module Foo :
    wire _foo_WIRE: UInt<1> @[foo.scala 0:0]
$ firtool foo.fir
foo.scala:0:0: error: sink "" not fully initialized in module "Foo"

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