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[WireDFT] Add support for wiring optional clock div bypass signal. #5219
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[WireDFT] Add support for wiring optional clock div bypass signal. #5219
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Nice.
It would be nice if the enable and bypass could be wired in one shot. However, that is a larger refactor. Future work? (I'd rather just remove this pass and replace it with a Chisel-side solution, though.)
Per reviewer feedback (and suggested code), thanks!! Note this tweaks the insertion point for the indexing to be as early as possible after the value is defined, to ensure its available (dominates) as much as needed.
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🥇
…5219) If a signal is annotated as the clock divider bypass signal, wire it to clock gates that have the expected port. Like test_en wiring the port number is hardcoded, but unlike test_en this ignores the "bypass" port if that port doesn't match the expected bypass port name/dir/type. Warning is emitted if looks compatible but name doesn't match and bypass signal annotation is found.
…5219) (#5225) If a signal is annotated as the clock divider bypass signal, wire it to clock gates that have the expected port. Like test_en wiring the port number is hardcoded, but unlike test_en this ignores the "bypass" port if that port doesn't match the expected bypass port name/dir/type. Warning is emitted if looks compatible but name doesn't match and bypass signal annotation is found.
If a signal is annotated as the clock divider bypass signal, wire it to clock gates that have the expected port.
Like
test_en
wiring the port number is hardcoded, but unlike test_en this ignores the "bypass" port if that port doesn't match the expected bypass port name/dir/type.Warning is emitted if looks compatible but name doesn't match and bypass signal annotation is found.