8000 [LowerSeqToSV] Remove Vivado workaround by uenoku · Pull Request #5245 · llvm/circt · GitHub
[go: up one dir, main page]
More Web Proxy on the site http://driver.im/
Skip to content

[LowerSeqToSV] Remove Vivado workaround #5245

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 3 commits into from
May 24, 2023
Merged

[LowerSeqToSV] Remove Vivado workaround #5245

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
3265c1c
[LowerSeqToSV] Remove Vivado workaround
uenoku May 23, 2023
4e9e7ed
Merge branch 'main' of github.com:llvm/circt into dev/uenoku/lower-se…
uenoku May 23, 2023
f9f48c0
Rebase
uenoku May 23, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 0 additions & 3 deletions include/circt/Dialect/Seq/SeqPasses.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -38,9 +38,6 @@ def LowerSeqFIRRTLToSV: Pass<"lower-seq-firrtl-to-sv", "hw::HWModuleOp"> {
let options = [
Option<"disableRegRandomization", "disable-reg-randomization", "bool", "false",
"Disable emission of register randomization code">,
Option<"addVivadoRAMAddressConflictSynthesisBugWorkaround",
"add-vivado-ram-address-conflict-synthesis-bug-workaround", "bool", "false",
"Add a vivado attribute to specify a ram style of array registers">,
Option<"emitSeparateAlwaysBlocks", "emit-separate-always-blocks", "bool", "false",
"Emit assigments to registers in separate always blocks">
];
Expand Down
9 changes: 5 additions & 4 deletions include/circt/Firtool/Firtool.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -206,10 +206,11 @@ struct FirtoolOptions {

llvm::cl::opt<bool> addVivadoRAMAddressConflictSynthesisBugWorkaround{
"add-vivado-ram-address-conflict-synthesis-bug-workaround",
llvm::cl::desc("Add a vivado specific SV attribute (* ram_style = "
"\"distributed\" *) to array registers as a workaronud "
"for a vivado synthesis bug that incorrectly modifies "
"address conflict behavivor of combinational memories"),
llvm::cl::desc(
"Add a vivado specific SV attribute (* ram_style = "
"\"distributed\" *) to unpacked array registers as a workaronud "
"for a vivado synthesis bug that incorrectly modifies "
"address conflict behavivor of combinational memories"),
llvm::cl::init(false), llvm::cl::cat(category)};

bool isRandomEnabled(RandomKind kind) const {
Expand Down
18 changes: 0 additions & 18 deletions lib/Dialect/Seq/Transforms/LowerSeqToSV.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -46,8 +46,6 @@ struct SeqFIRRTLToSVPass
: public impl::LowerSeqFIRRTLToSVBase<SeqFIRRTLToSVPass> {
void runOnOperation() override;
using LowerSeqFIRRTLToSVBase<SeqFIRRTLToSVPass>::disableRegRandomization;
using LowerSeqFIRRTLToSVBase<
SeqFIRRTLToSVPass>::addVivadoRAMAddressConflictSynthesisBugWorkaround;
using LowerSeqFIRRTLToSVBase<SeqFIRRTLToSVPass>::emitSeparateAlwaysBlocks;
using LowerSeqFIRRTLToSVBase<SeqFIRRTLToSVPass>::LowerSeqFIRRTLToSVBase;
using LowerSeqFIRRTLToSVBase<SeqFIRRTLToSVPass>::numSubaccessRestored;
Expand Down Expand Up @@ -144,11 +142,8 @@ namespace {
class FirRegLower {
public:
FirRegLower(hw::HWModuleOp module, bool disableRegRandomization = false,
bool addVivadoRAMAddressConflictSynthesisBugWorkaround = false,
bool emitSeparateAlwaysBlocks = false)
: module(module), disableRegRandomization(disableRegRandomization),
addVivadoRAMAddressConflictSynthesisBugWorkaround(
addVivadoRAMAddressConflictSynthesisBugWorkaround),
emitSeparateAlwaysBlocks(emitSeparateAlwaysBlocks){};

void lower();
Expand Down Expand Up @@ -211,7 +206,6 @@ class FirRegLower {
hw::HWModuleOp module;

bool disableRegRandomization;
bool addVivadoRAMAddressConflictSynthesisBugWorkaround;
bool emitSeparateAlwaysBlocks;
};
} // namespace
Expand Down Expand Up @@ -581,17 +575,6 @@ FirRegLower::RegLowerInfo FirRegLower::lower(FirRegOp reg) {
// Move Attributes
svReg.reg->setDialectAttrs(reg->getDialectAttrs());

// For array registers, we annotate ram_style attributes if
// `addVivadoRAMAddressConflictSynthesisBugWorkaround` is enabled so that we
// can workaround incorrect optimizations of vivado. See "RAM address conflict
// and Vivado synthesis bug" issue in the vivado forum for the more detail.
if (addVivadoRAMAddressConflictSynthesisBugWorkaround &&
hw::type_isa<hw::ArrayType, hw::UnpackedArrayType>(reg.getType()))
circt::sv::setSVAttributes(
svReg.reg,
sv::SVAttributeAttr::get(builder.getContext(), "ram_style",
R"("distributed")", /*emitAsComment=*/false));

if (auto innerSymAttr = reg.getInnerSymAttr())
svReg.reg.setInnerSymAttr(innerSymAttr);

Expand Down Expand Up @@ -781,7 +764,6 @@ void SeqToSVPass::runOnOperation() {
void SeqFIRRTLToSVPass::runOnOperation() {
hw::HWModuleOp module = getOperation();
FirRegLower firRegLower(module, disableRegRandomization,
addVivadoRAMAddressConflictSynthesisBugWorkaround,
emitSeparateAlwaysBlocks);
firRegLower.lower();
numSubaccessRestored += firRegLower.numSubaccessRestored;
Expand Down
2 changes: 0 additions & 2 deletions lib/Firtool/Firtool.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -213,8 +213,6 @@ LogicalResult firtool::populateHWToSV(mlir::PassManager &pm,
pm.nest<hw::HWModuleOp>().addPass(seq::createSeqFIRRTLLowerToSVPass(
{/*disableRandomization=*/!opt.isRandomEnabled(
FirtoolOptions::RandomKind::Reg),
/*addVivadoRAMAddressConflictSynthesisBugWorkaround=*/
opt.addVivadoRAMAddressConflictSynthesisBugWorkaround,
/*emitSeparateAlwaysBlocks=*/
opt.emitSeparateAlwaysBlocks}));
pm.addPass(sv::createHWMemSimImplPass(
Expand Down
2 changes: 0 additions & 2 deletions test/Dialect/Seq/firreg.mlir
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
// RUN: circt-opt %s -verify-diagnostics --lower-seq-firrtl-init-to-sv --lower-seq-firrtl-to-sv | FileCheck %s --check-prefixes=CHECK,COMMON
// RUN: circt-opt %s -verify-diagnostics --pass-pipeline="builtin.module(lower-seq-firrtl-init-to-sv, hw.module(lower-seq-firrtl-to-sv{disable-reg-randomization}))" | FileCheck %s --check-prefix COMMON --implicit-check-not RANDOMIZE_REG
// RUN: circt-opt %s -verify-diagnostics --pass-pipeline="builtin.module(lower-seq-firrtl-init-to-sv, hw.module(lower-seq-firrtl-to-sv{add-vivado-ram-address-conflict-synthesis-bug-workaround}))" | FileCheck %s --check-prefixes=CHECK,VIVADO
// RUN: circt-opt %s -verify-diagnostics --pass-pipeline="builtin.module(lower-seq-firrtl-init-to-sv, hw.module(lower-seq-firrtl-to-sv{emit-separate-always-blocks}))" | FileCheck %s --check-prefixes SEPARATE

// COMMON-LABEL: hw.module @lowering
Expand Down Expand Up @@ -381,7 +380,6 @@ hw.module private @init1DVector(%clock: i1, %a: !hw.array<2xi1>) -> (b: !hw.arra
%r = seq.firreg %a clock %clock sym @__r__ : !hw.array<2xi1>

// CHECK: %r = sv.reg sym @[[r_sym:[_A-Za-z0-9]+]]
// VIVADO: "ram_style" = "\22distributed\22"

// CHECK: sv.always posedge %clock {
// CHECK-NEXT: sv.passign %r, %a : !hw.array<2xi1>
Expand Down
0