10000 [ExportVerilog] Ensure DivS/ModS are signed regardless of context. by dtzSiFive · Pull Request #6966 · llvm/circt · GitHub
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[ExportVerilog] Ensure DivS/ModS are signed regardless of context. #6966

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Merged
merged 1 commit into from
Apr 30, 2024
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[ExportVerilog] Ensure DivS/ModS are signed regardless of context. #6966

merged 1 commit into from
Apr 30, 2024

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dtzSiFive
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Fixes #6961.

@dtzSiFive
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dtzSiFive commented Apr 30, 2024 •
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Have not confirmed this fixes the issue in EDA playground, and would be good to confirm w/ModS (and put under test).

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Poked a bit, this maybe shows this: https://www.edaplayground.com/x/CEdZ maybe -- dropping the {1'h0, ....} part else they're the same.

seldridge
seldridge approved these changes Apr 30, 2024
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This looks like the right fix. 👍

test/Conversion/ExportVerilog/hw-dialect.mlir
Comment on lines -460 to +461
// CHECK: assign awire = 4'sh5 / -4'sh3;
// CHECK: assign awire = $signed(4'sh5 / -4'sh3);
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🥲 It's unfortunate that this shows up. However, to know that this can be elided would mean teaching ExportVerilog about context sensitive widths. This would be a huge pain and it's better to just do the safe, cheap thing. (If non-obvious, this is commentary and non-blocking.)

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Agree about a ModS test. This would be good to have under an integration test. That can be handled on the Chisel side.

uenoku
uenoku approved these changes Apr 30, 2024
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LGTM, thank you for fixing this. Glad that the simple change fixes the issue :)

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Mod acting similarly: https://www.edaplayground.com/x/Qzbs . Integration test Chisel-side works for me.

Change to output for ModS is included in test.

@dtzSiFive dtzSiFive merged commit 3ef492c into llvm:main Apr 30, 2024
@dtzSiFive dtzSiFive deleted the fix/issue-6961 branch April 30, 2024 12:07
@dtzSiFive dtzSiFive mentioned this pull request Apr 30, 2024
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@seldridge seldridge seldridge approved these changes

@uenoku uenoku uenoku approved these changes

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[FIRRTL][ExportVerilog] Signed Division Bug
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@dtzSiFive @seldridge @uenoku
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