[ImportVerilog] Support for loop variables #7393
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Add support for variables declared inside the for loop initializer, such as `for (int x = 0; ...)`. This is pretty straightforward, since Slang already creates corresponding variable declaration AST nodes in the surrounding scope. The only change needed is removing an error diagnostic.
maerhart
approved these changes
Jul 27, 2024
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Add support for variables declared inside the for loop initializer, such as
for (int x = 0; ...). This is pretty straightforward, since Slang already creates corresponding variable declaration AST nodes in the surrounding scope. The only change needed is removing an error diagnostic.