[LoongArch] Enable interleaved memory accesses by default #141555
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@llvm/pr-subscribers-backend-loongarch Author: None (tangaac) ChangesFull diff: https://github.com/llvm/llvm-project/pull/141555.diff 1 Files Affected:
diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h b/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h
index d43d2cb0eb124..dc0478daeb6af 100644
--- a/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h
@@ -52,6 +52,7 @@ class LoongArchTTIImpl : public BasicTTIImplBase<LoongArchTTIImpl> {
unsigned getCacheLineSize() const override;
unsigned getPrefetchDistance() const override;
bool enableWritePrefetching() const override;
+ bool enableInterleavedAccessVectorization() const override { return true; }
// TODO: Implement more hooks to provide TTI machinery for LoongArch.
};
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