8000 [RV64_DYNAREC] Fixed some opcodes caught by cosim by xctan · Pull Request #1561 · ptitSeb/box64 · GitHub
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[RV64_DYNAREC] Fixed some opcodes caught by cosim #1561

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Merged
merged 17 commits into from
Jun 6, 2024
Merged

[RV64_DYNAREC] Fixed some opcodes caught by cosim #1561

merged 17 commits into from
Jun 6, 2024

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xctan
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@xctan xctan commented Jun 5, 2024

No description provided.

ksco
ksco reviewed Jun 5, 2024
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@xctan xctan marked this pull request as draft June 6, 2024 04:22
@xctan xctan marked this pull request as ready for review June 6, 2024 11:01
@xctan xctan marked this pull request as draft June 6, 2024 12:36
@xctan xctan marked this pull request as ready for review June 6, 2024 13:16
@ptitSeb
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ptitSeb commented Jun 6, 2024

So it's ready to merge?

ptitSeb
ptitSeb reviewed Jun 6, 2024
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@xctan
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xctan commented Jun 6, 2024

So it's ready to merge?

Yup. I cannot find any other prominent differences between dynarec and the interpreter when running VMP with cosim.

@ptitSeb ptitSeb merged commit 75004d0 into ptitSeb:main Jun 6, 2024
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Javier97sm pushed a commit to Javier97sm/box64 that referenced this pull request Aug 16, 2024
@xctan @Javier97sm
[RV64_DYNAREC] Fixed some opcodes caught by cosim (ptitSeb#1561)
4917bd3 
* [RV64_DYNAREC] Fixed emit_shrd16c

* [RV64_DYNAREC] Fixed BSWAP Gw

* [RV64_DYNAREC] Fixed 32 bit RCL/RCR Ed, 1

* [RV64_DYNAREC] Fixed 32 bit BTR

* [RV64_DYNAREC] Fixed 32 bit SHLD

* [RV64_DYNAREC] Fixed 32 bit SHLD again

* [RV64_DYNAREC] Fixed 16 bit constant SHLD again

* [RV64_DYNAREC] Fixed 16-bit BTC

* [RV64_DYNAREC] Fixed 32-bit rotates using Zbb extension

* [RV64_DYNAREC] Fixed 16-bit SHLD opcode

* [RV64_DYNAREC] Fixed the mask of LAHF opcode

* [RV64_DYNAREC] Fixed LAHF again and handled OF2 before cosim

* [RV64_DYNAREC] Fixed XADD Eb, Gb when Eb == Gb

* [RV64_DYNAREC] Fixed XADD Ew, Gw when Ew == Gw

* [RV64_DYNAREC] Fixed zero extension of 32 bit Ed operand

* [RV64_DYNAREC] Fixed XADD Eb, Gb again for AH, BH, CH, DH

* [RV64_DYNAREC] Fixed various 16-bit immediate extension
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