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A visual hashing library with Emojis 🪁 ⛓️ 🌐 🚜

TypeScript 4 Updated Feb 1, 2021

This project contains the tools necessary to run iLO 3/4/5 remote consoles directly from linux, provides ssh scripts to connect via terminal and for iLO 3 it provides proxy scripts to make modern b…

Shell 43 4 Updated Aug 31, 2024

All Digital Phase-Locked Loop

Tcl 11 1 Updated May 22, 2023

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

VHDL 616 53 Updated Apr 4, 2025

Qml Color Picker, Color Wheel, Color Tool, Color History

QML 21 3 Updated Nov 19, 2024

Qml Color Picker, Color Wheel, Color Tool, Color History

C++ 1 Updated Jan 22, 2024

Ribbon Control for Qt

C++ 1 Updated Feb 27, 2024

QML toolkit library. Reusable UI components

QML 22 9 Updated Feb 22, 2025

Magic VLSI Layout Tool

C 539 117 Updated May 17, 2025

The Computer History Simulation Project

C 1,739 302 Updated May 10, 2025

A collection of scripts and tools for Atmel ATF150x and GAL Programmable logic devices, some of the only standing active 5V programmable logic parts still available.

Python 99 12 Updated May 18, 2025

GAL chip programmer for Arduino

C 186 51 Updated May 20, 2025
Verilog 17 4 Updated Oct 26, 2022

KLayout Main Sources

C++ 897 222 Updated May 22, 2025

SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

Python 454 80 Updated May 14, 2025

A High-performance Timing Analysis Tool for VLSI Systems

Verilog 621 153 Updated May 26, 2023
C++ 69 35 Updated May 22, 2025

Place and route tool for FPGAs

C++ 420 72 Updated Jul 28, 2019

Documenting the Xilinx 7-series bit-stream format.

Python 799 156 Updated May 17, 2025

Experimental flows using nextpnr for Xilinx devices

C++ 236 47 Updated Oct 11, 2024

nextpnr portable FPGA place and route tool

C++ 1,439 257 Updated May 22, 2025

RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA

C++ 90 20 Updated Feb 11, 2020

Verilog to Routing -- Open Source CAD Flow for FPGA Research

C++ 1,097 414 Updated May 23, 2025

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using…

Verilog 159 57 Updated May 11, 2023

Qflow full end-to-end digital synthesis flow for ASIC designs

C 211 38 Updated Oct 26, 2024

An abstraction library for interfacing EDA tools

Python 687 202 Updated May 5, 2025

FuseSoC standard core library

138 37 Updated Apr 2, 2025

VHDL 2008/93/87 simulator

VHDL 2,559 383 Updated May 21, 2025
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